1. Variation-Aware Design for Nanoscale VLSI Sachin S. Sapatnekar University of Minnesota CAS-FEST 2010 Circuits and Systems Forum on Emerging and Special Topics 1

2. The proliferation of computing Tablets Entertainment Smart grid Healthcare, automotive, security, …

3. More computing everywhere… 3

4. The incredibly shrinking transistor 4 Electronics, Vol. 38, No. 8, Apr 19, 1965

5. Cost of going to a new technology [GLOBALFOUNDRIES] 5

6. So why bother? Because it makes economic sense… –R&D costs are rising, but so is revenue 6 [GLOBALFOUNDRIES]

7. 7 New technologies: 3D ICs SOI wafers with bulk substrate removed Adapted from [Das et al., ISVLSI, 2003] by B. Goplen Generalized view Bulk wafer Metal level of wafer 1 Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Bulk Substrate Detailed view Inter-layer bonds Device level 1 500  m 10  m 1m1m Interlayer Via Through-silicon Vias (TSVs)

8. New technologies: near-threshold computing 8 [Dreslinski et al.]

9. Types of variations Based on the model –Systematic –Random –“Random” Based on the source –Process –Environmental –Design Uncertainty Based on the time when they are seen –One-time variations –Run-time variations 9

10. Process-related variations: examples Channel width variation: poly/ diff rounding, misalignment Gale oxide thickness Random dopant fluctuations Poly Diffusion Source: S. Tyagi Uniform Non-uniform Source: S. Borkar Many of these variations can be modeled by Gaussians 10 Source: Pey&Tung

11. A taxonomy of variations (contd.) Within-Die (WID) Variations Systematic Die-to-Die (D2D) Variations Random [Intel] Lot-to-Lot Die-to-Die Wafer-to-Wafer 11

12. The (f)law of averages [The drunk skater problem] 12 http://www.stanford.edu/~savage/flaw/

13. Why is this important? Because it affects circuit timing… … and power 13

14. Aging effects Circuit behaviour degrades with time NBTI Electromigration Oxide breakdown Hot carrier injection 14 SiH + h + → Si + + ½H 2 SiH H H H2H2 Substrate PolyGate Oxide [S. Sjøthun] [Suto, Teradyne] Time Failure rate 7-15 years 1-40 weeks Normal lifetime  Constant failure rate  Based on TDDB, EM, hot-electrons…

15. Environmental variations Supply voltage Soft errors 15 Source: Automotive 7-8, 2004 1

16. Environmental variations: Temperature [Chu 1999] [Joshi] By Trubador, available at http://www.phys.ncku.edu.tw/~htsu/humor/fry_egg.html Fried egg [Intel] [IBM]

17. Technology trends [Chu 1999] [Joshi] By Trubador, available at http://www.phys.ncku.edu.tw/~htsu/humor/fry_egg.html Fried egg Core Cache70ºC 120ºC [Intel] Adapted from [Das et al., ISVLSI, 2003] Generalized view Bulk wafer Metal level of wafer 1 Tier 1 Tier 2 Tier 3 Tier 4 Tier 5 Bulk Substrate Detailed view Intertier bonds Device level 1 500  m 10  m 1m1m Intertier Via SOI wafers with bulk substrate removed

18. Overcoming variations Three-pronged strategy –Reduce the fundamental sources –Don’t allow them to be expressed (design around the effects) –Mitigate the effects Example: temperature effects –Low-power design –Design to reduce T –Design to mitigate T-driven degradation All all levels of abstraction, using all available methods –Design –CAD –Architecture/OS –Algorithms 18

19. Adaptive sensing/mitigation Sense/adapt feedback loops Guardbanded presilicon fixes vs. adaptive postsilicon fixes Monitor cores Canary circuits –Silicon odometer Razor, CRISTA, etc. 19 LUT Sensor DC-DC Converter FBB Generator v bp v bn V dd Circuit Block Guardbanding Sensor-driven Phase Comp.... A B C PC_OUT (freq=f ref - f stress ) [Kim, Minnesota]

20. CAS-FEST 2010 A Resilience Roadmap –Sani Nassif, IBM Mitigating Variability in Near-Threshold Computing –Dennis Sylvester, Univ. of Michigan Robust System Design to Overcome CMOS Reliability Challenges –Subhasish Mitra, Stanford Univ. Computer Aided Circuit Design for Reliability in Nanometer CMOS –Georges Gielen, Katholieke Univ. – Leuven Process Compensated High Speed Ring Oscillators in Sub-Micron CMOS –Alyssa B. Apsel, Cornell U. Containing the Nanometer Pandora-box: Design Techniques for Variation-Aware Low-Power Systems –Abhijit Chatterjee, Georgia Tech. 20