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Circuit Research Lab, Intel

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Presentation on theme: "Circuit Research Lab, Intel"— Presentation transcript:

1 Circuit Research Lab, Intel
Impact of Variation Sources on Circuit Performance and Power & Design Techniques for Variation Tolerance Keith A. Bowman Circuit Research Lab, Intel April 18, 2006

2 Outline Technology Trends Sources of Variability
Impact of Variations on Circuit Design Variation Tolerance & Control Variation Compensation Techniques So, what should we do? Here is a list of topics and questions that the panel and audience can ponder and discuss. Clearly, we should attack the problem at all levels – architecture and systems, circuits and design, test and process technology. Read through the list… So, what do we do in the future? Let us ask the experts…

3 Technology Outlook

4 Technology Trends More transistors per chip
Deliver higher performance systems Power is the limiter Larger delay and power variability

5 Sources of Variability
Process Circuit Operation Simulation Tools Channel Length Temperature Timing Analysis Channel Width Supply Voltage RC Extraction Threshold Voltage Aging (NBTI) Cell Modeling I-V Curves Overlap Capacitance Cross-Coupling Capacitance Circuit Simulations Interconnect Multiple Input Switching Process Files Transistor Models

6 Scale of Variations Die-to-Die (D2D) Variations
Within-Die (WID) Variations Systematic Random Wafer Scale Die Scale Feature Scale

7 Sub-Wavelength Lithography
WID became significant at 250nm generation Gate Length < Litho Wavelength (l=248nm)

8 Gate Length Variation Die-to-Die Variation
Examples: Processing temperatures, equipment properties, polishing, wafer placement, resist thickness Systematic Within-Die Variation Long range WID variation (e.g., mm range) Variation depends on correlation distance Variation profile varies randomly Examples: Lens aberrations, mid-range flare, stepper non-uniformities, scanner overlay control, multiple dies per reticle, wafer topography Random Within-Die Variation Short range WID variation Fluctuates independent of device location Examples: Patterning limitations, short-range flare, line edge roughness Source: Steve Duvall Source: Nagib Hakim

9 Systematic-WID Variation
Source: H. Masuda, et al., IEEE CICC 2005. From circuit design perspective, systematic WID behaves as a correlated random-WID variation

10 Gate Length Variation Trends
=248nm =193nm Total CD control ~ fixed % of nominal gate length Random variations increase with scaling

11 Systematic-WID Correlation Length
=248nm =193nm

12 Poly/Diffusion Rounding and Misalignment
Channel Width Variation Poly/Diffusion Rounding and Misalignment Poly Xtr 2 Xtr 1 Diffusion Source: S. Tyagi

13 Threshold Voltage Variation

14 Random Dopant Fluctuation
Source: X. Tang

15 Interconnect Variations
Depth of Focus Variation Optical Proximity Correction (OPC) resizes interconnect widths to guarantee printability Depends on neighboring interconnects Chemical Mechanical Polishing (CMP) Depends on local area metal density Metal density requirements significantly reduce variation Etching Variation expected to be smaller than depth of focus & CMP variation

16 Impact of OPC on Isolated Lines
Bossung Plot Example (Isolated Drawn Lines) Light Source CD Max CD 150nm Chip Topography 100nm Focus Variations Min CD FN2 FP2 Focus Focus Window

17 Temperature & Supply Voltage
Deterministic Variation Die Maps Junction Temperature Supply Voltage (IR Drop) Source: G. Yuan

18 Supply Voltage Variations
Chip activity change Current delivery RLC Dynamic: ns to us

19 Negative Bias Temperature Instability (NBTI)
Aging (NBTI) Negative Bias Temperature Instability (NBTI) Source: M. Agostinelli, et al., IEEE Intl. Reliability Physics Symp., 2005. PMOS VT degrades from bias & temperature stress Impact of NBTI depends on gate area

20 Cost of Variations Overestimating Variations
Increases design time Larger die size Rejection of otherwise good design options Missed market windows Increases design effort Underestimating Variations Functional yield loss Performance reduction Increases silicon debug time Increases manufacturing effort

21 Ncp  Number of Independent Critical Paths
Impact of WID Variations Ncp  Number of Independent Critical Paths As Ncp increases, WID distribution mean increases and variance decreases

22 Impact of WID & D2D Variations
Model: Only WID Variations Model: Only D2D Variations Model: D2D & WID Variations Mean FMAX Reduction Measured Data WID variations primarily impact FMAX mean D2D variations primarily impact FMAX variance

23 Impact of WID & D2D Variations
WID Distribution Nominal Leakage D2D Distribution D2D & WID Distribution WID variations impact leakage median D2D variations impact leakage variance

24 FMAX Binning Performance & Power Variation Range FMAX ~30% Leakage ~5X
Power & Burn-In Limit Variation Range FMAX ~30% Leakage ~5X

25 Deeper Pipelines

26 Impact of Logic Depth Critical Path Systematic-WID Variations (r=1)
Random-WID Variations Random-WID variation averages across N stages

27 Impact on Logic Depth Deeper pipeline
Impact of random WID grows with deeper pipelining Impact of systematic WID insensitive to pipelining

28 Impact of Steep Speedpath Walls
0% 5% 10% 15% 20% 10 100 200 1000 10000 # critical paths % mean Fmax loss Mean FMAX reduces as a logarithmic function of NCP

29 Freelance layout of the past…
Vss Vdd Op Ip Vss Vdd Op No layout restrictions

30 Transistor orientation restrictions
Vss Vdd Op Vss Vdd Op Ip

31 Transistor width quantization
Vdd Vdd Ip Op Op Vss Vss

32 Today’s unrestricted routing…

33 Future metal restrictions

34 Dense layout causes hot-spots
Today’s metric… Maximize Transistor Density Dense layout causes hot-spots

35 Optimizing Transistor & Power Density
Tomorrow’s metric… Optimizing Transistor & Power Density Balanced Design

36 Supply & Body Bias Knobs

37 Without adaptive supply
0% 20% 40% 60% 80% 100% 0.9 0.95 1 1.05 Frequency Bin Die count

38 Adaptive Body Bias (ABB)

39 Reduce Impact of D2D Variations
Static Adaptive Biasing Reduce Impact of D2D Variations Power limit: 110oC Adaptive supply: lower Vcc ABB: reverse body bias ABB: forward body bias Adaptive supply: nothing

40 Effectiveness of Adaptive Biasing

41 Effectiveness of Adaptive Biasing
Slower Parts (Lower Power) Leakage is a small percentage of total power Trade-off leakage increase for performance gain More effective to apply a forward body bias (FBB) Faster Parts (Higher Power) Active and leakage contribute significantly to total power Vcc reduction lowers both active and leakage power More effective to reduce supply voltage

42 Static ABB for WID Variations
WID ABB Concept WID ABB Effectiveness 150nm technology testchip Clock distribution network Adaptive supply + ABB Body bias 3 Adaptive supply + WID ABB Body bias 1 200% more chips in highest bin Body bias 2 No body bias for clock Needs triple-well process

43 Summary Technology trends are expected to amplify circuit performance & power variability As technology scales, number of variation sources are increasing WID variations impact FMAX mean & leakage median D2D variations impact FMAX & leakage variances Adaptive techniques enable opportunity to mitigate impact of D2D & WID variations So, what should we do? Here is a list of topics and questions that the panel and audience can ponder and discuss. Clearly, we should attack the problem at all levels – architecture and systems, circuits and design, test and process technology. Read through the list… So, what do we do in the future? Let us ask the experts…

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