1. Built-In Self-Test/Self-Diagnosis for RAMs
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Jhongli, Taiwan

2. Outline Introduction Fault Models and Test Algorithms
Memory BIST/BISD Design
BIST Design
BISD Design
Memory Diagnosis
Fault Diagnosis
Defect Diagnosis

3. Introduction
Modern system-on-chip (SOC) designs typically consist of hundreds of memories
Memories usually dominate the chip area
Furthermore, memories are designed with the aggressive design rules such that they are prone to defects
Thus the memory yield heavily impacts the SOC yield
Increasing memory yield can significantly increase the SOC yield
Yield-enhancement techniques for memories
Diagnosis & repair

4. SOC Yield Yield of an SOC For example, UltraSparc chip yield
Improve the yields of memories can drastically increase the yields of SOCs
For example, UltraSparc chip yield
Source: R. Rajsuman, IEEE D&T, 2001

5. Yield Learning Curve Yield Time Diagnosis/repair Repair Mature phase
Early phase
Intermediate phase
Time

6. Testing and Repair of RAMs in SOCs
16-core SPARC (Oracle)
Niagara2 (Sun)
POWER6 (IBM)
DFT features:
Scan test + test compression
Programmable memory built-in self-test (MBIST) + repair
SerDes internal and external look-back tests
DFT features:
32 Scans + ATPG
BIST for arrays ….
DFT features:
Logic BIST
BIST for arrays
BISR for arrays …

7. Fault Models and Test Algorithms

8. Conclusions
Undoubtedly, 3D RAM will be one pioneer product using 3D integration technology
Some differences exist between a 2D RAM and a 3D RAM with TSVs
Those differences incur some challenges on the testing and repair of 3D RAMs
Effective testing and repair techniques thus are imperative for the production of 3D RAMs
Due to the uncertainty of a 3D RAM
DFT/DFY/DFR techniques with the feature of adaptability is one main trend