1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose This course provides an overview of the peripheral functions that are built into M16C series microcontrollers (MCUs). Objectives  Learn about the features and operation of the Analog-to-Digital converter, Digital-to-Analog converter, DMA Controller, CRC calculation circuit, and Watchdog Timer.  Understand the basics of the interrupts M16C MCUs provide.  Discover how the clock generation circuit and voltage detection circuit operate. Content 24 pages 4 questions Learning Time 38 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved 2 Analog-to-Digital Converter Successive-approximation A/D converter circuit 24 channels 10-bit or 8-bit resolution, selectable Built-in Sample & Hold Five operating modes: - One Shot - Repeat - Single Sweep - Repeat Sweep, Modes 0 and 1

3. © 2008, Renesas Technology America, Inc., All Rights Reserved 3 Successive-Approximation Circuit Clock Divider Circuit ¸1, ¸2, ¸¸3, ¸4, ¸6, ¸12 fAD Successive conversion register VREF AVss VCUT=0 Decoder for A-D Register AD0 Register AD1 Register AD2 Register AD3 Register AD4 Register AD5 Register AD6 Register AD7 Register ADCON1 ADCON0 Data Bus High Order Data Bus Low Order Multiplexor Decoder for channel selection AN00-07 AN20-27 AN0-7 ANEX0 ANEX1 Comparator Vref Vin ADCON2 Decoder for channel selection Multiplexor Resistor Ladder R-2R Resistor Ladder AD0 Register AD1 Register AD2 Register AD3 Register AD4 Register AD5 Register AD6 Register AD7 Register

4. © 2008, Renesas Technology America, Inc., All Rights Reserved 4 A/D Operating Modes ModeDescription One Shot modeOne analog input channel is converted to a digital value once. The conversion is stopped when it is completed or if the Start flag is set back to zero. At the end of the conversion, an interrupt request can be generated. Repeat modeContinuous conversions can be performed on an analog input. The conversion is stopped by clearing the AD Conversion Start flag. No interrupt request is generated in this mode. Single Sweep modeThe input voltages on selected pins are converted once, one at a time. You select the signals to be converted using the ADCON0 and ADCON1 registers. Conversion is ended by clearing the ADST bit to 0 or when the conversion is complete. An end-of-conversion interrupt can be generated. Repeat Sweep modesThe analog signals on multiple channels are converted to digital values repeatedly, one at a time. This mode actually encompasses two modes: modes 0 and 1, which we will discuss on the next page.

5. © 2008, Renesas Technology America, Inc., All Rights Reserved 5 A/D Sweep Modes Sa Sa Sa AN0 AN1 AN2 AN3 AN6 AN4 AN5 AN7 8/10-bit M16C ADC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

7. © 2008, Renesas Technology America, Inc., All Rights Reserved 7 Digital-to-Analog Converter R-2R type D/A converter Two separate independent converters 8-bit resolution Voltage reference (VREF) input is available so the output value can be easily scaled. Control register DA register

8. © 2008, Renesas Technology America, Inc., All Rights Reserved 8 Direct Memory Access Controller Two DMAC channels Transfers  Any fixed address to/from the 1MB space  Any fixed address to/from fixed address Transfers can be up to 128KB (16-bit) or 64KB (8-bit) Request sources  INT0/1, SI/O3, SI/O4  Timers A0-A4, B0-B5  UART0-2, A/D, Software Trigger 8-bit and 16-bit transfer units Single and Repeat transfer modes Cycle-steal operation

9. © 2008, Renesas Technology America, Inc., All Rights Reserved 9 Single and Repeat Transfers Single Transfer  A byte (8-bit) or word (16-bit) is transferred per request.  Transfers stop when: - DMAC channel is disabled (DMAE set to “0”). - DMAi transfer counter underflows when the terminal count is reached. Repeat Transfer  A byte (8-bit) or word (16-bit) is transferred per request.  When the DMAi counter underflows, it is reloaded with the value of DMAi transfer counter reload register, then DMAC transfers continue.  Transfers stop when: - DMAC channel is disabled (DMAE set to “0”).

10. © 2008, Renesas Technology America, Inc., All Rights Reserved 10 CRC Circuit Cyclic Redundancy Check circuit generates checksum (CRC value) for a block of data that can be used to detect errors in the data. 16-bit CRC value is generated from 8-bit values (bytes) input to CRC circuit. Dedicated hardware CRC circuit consists of two registers:  CRCD: 16-bit register that contains the calculated CRC  CRCIN: 8-bit register that is loaded with the 8-bit data used to produce the CRC CRC circuits in M16C MCUs use CRC-CCITT generator polynomial (X 16 + X 12 + X 5 + 1) to calculate CRC value. CRC code generation takes two cycles per byte of data.

11. © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Watchdog Timer WDT can Reset MCU if application software goes out of control. - In Watchdog Reset mode, the WDT counter value must be re-written periodically by user application to prevent underflows. 15-bit counter Clock sources include the CPU clock, PLL clock, and ring oscillator. Two operating modes: - Interrupt request—When counter underflows, an interrupt is generated. - Reset request—When counter underflows, MCU is reset. Watchdog Timer interrupt request Reset 1/16 Ring oscillator circuit Pre-scaler PM22=0 PM22=1 CPU Clock /HOLD /RESET Write to WDTS register PM12=0 PM22=0 Set to H’7FFF

13. © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Interrupts M16C MCUs support software and hardware interrupt types. Interrupt Software (Non-maskable interrupt) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Hardware NMI /DBC (debug tools only) Watchdog Timer Oscillation stop and re-oscillation detection Single step (debug tools only) Address match Special (Non-maskable interrupt) Peripheral function (Maskable interrupt)

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Software Interrupts InterruptsDescription Overflow interruptOccurs when executing the INTO instruction with the “O” flag set. The “O” flag is changed by arithmetic. If the “O” bit in the CPU’s FLG register is set to “1” when the INTO (“O” test instruction) is executed, then the Overflow interrupt will be generated. The “O” bit can be set by the following arithmetic instructions: ABS, ADC, ADCF, ADD, CMP, DIV, DIVX, NEG, RMPA, SBB, SHA, and SUB. BRK interruptThe BRK interrupt occurs when the “BRK” instruction is executed. This instruction is useful in debugging applications where it implements breakpoint functionality. INT instruction interrupt (also known as a software trap) When the INT instruction with an interrupt vector number is executed, the corresponding vector is read and the relevant interrupt service routine (ISR) executes. The INT or trap interrupt can be used to generate a software interrupt that is particularly useful in real-time operating system (RTOS) implementations for task switching. Undefined instruction interrupt The Undefined instruction interrupt occurs when executing the UND instruction.

15. © 2008, Renesas Technology America, Inc., All Rights Reserved 15 Hardware Interrupts Special, non-maskable interrupts  NMI is generated when NMI pin changes from high to low.  Voltage-down detection is provided by LVD circuit.  Watchdog Timer is generated when WDT operates in interrupt request mode.  Oscillation stop and re-oscillation detection are provided by the clock generation circuit.  DBC is normally only used by development tools.  Single step is normally only used by development tools.  Address match is generated immediately before an instruction whose address matches a specified value. Peripheral function interrupts, maskable  Generated by timers, A/D, and other on-chip functions

16. © 2008, Renesas Technology America, Inc., All Rights Reserved 16 Interrupt Characteristics An interrupt vector (4 bytes) contains the start of that interrupt’s interrupt service routine (ISR). Part of the vector table is fixed (addresses 0xFFFDC to 0xFFFF) and contains the software interrupt vectors and special non-maskable hardware interrupt vectors. The remaining vectors can be located elsewhere in the memory; start address of the table is loaded into CPU’s INTB register. There are eight priority levels: 0 to 7 (lowest to highest). Interrupt sequence: 1.CPU clears interrupt’s IR flag to “0”. 2.CPU FLG register stored in CPU temporary register. 3.FLG registers configured as follows: I = 0, D = 0, U = 0 (unless INT for interrupts 32 to 63). 4.CPU temporary register and PC are copied to stack. 5.Interrupt’s priority level is set in the CPU’s IPL register. 6.PC is loaded with the address of the ISR

18. © 2008, Renesas Technology America, Inc., All Rights Reserved 18 Clock Generation Circuit The M16C clock generation circuit contains four oscillator circuits. Main clock oscillation circuit Sub-clock oscillation circuit Ring oscillator PLL frequency synthesiser Use of clock Clock frequency Usable oscillator Oscillator stop, restart function Other CPU clock source Peripheral function clock source 0 to 16MHz Ceramic oscillator Crystal osc. Presence Oscillator status after reset Oscillating Externally derived clock can be input CPU clock source Timer A, Timer B clock source 32kHz Crystal oscillator Pins to connect to oscillator Xin, Xout Presence Stopped CPU clock source Peripheral function clock source CPU & peripheral clock source when main clock stops About 1MHz - - Presence Stopped - Presence Stopped - - - CPU clock source Peripheral function clock source 10 to 24MHz

19. © 2008, Renesas Technology America, Inc., All Rights Reserved 19 Clock Circuit and Normal Mode  Three Modes: Normal, Wait, and Stop  Normal operating mode has 7 sub-modes : - High-speed- PLL operation - Medium-speed- Low-speed - Low-power dissipation- Ring oscillator - Ring oscillator low-power dissipation Sub-clock generator PLL 1/2 aebc d Frequency Divider 1/21/41/81/16 1/32 Main clock generator Ring oscillator Osc. stop, re-start detection Clock Generation Circuit of M16C MCUs

20. © 2008, Renesas Technology America, Inc., All Rights Reserved 20 Clock Circuit - Wait Mode In Wait mode, the CPU clock is turned off to save power. Peripherals can be supplied by the main clock, sub-clock, ring oscillator, and PLL clock. Main clock supply to the peripheral functions can be switched off and the peripherals can be driven from the 32kHz sub-clock. Wait mode is entered by executing the WAIT instruction. Disabling the PLL before entering Wait mode further reduces power consumption. Pin states during Wait mode are defined. (Specific details can be found in the M16C hardware manuals.) Wait mode is exited by a hardware reset, NMI, or peripheral interrupt.

21. © 2008, Renesas Technology America, Inc., All Rights Reserved 21 Clock Circuit - Stop Mode In Stop mode, all oscillator clocks are stopped. The CPU and the peripherals supplied from these clocks also stop. Any peripherals supplied by external clocks continue to operate. This mode minimizes power consumption. If the Vcc pins are supplied with a voltage ≥V RAM, the contents of the internal RAM are retained. Stop mode is entered by turning all clocks off by setting the CM10 bit in the CM1 register to “1”. Pin states during Stop mode are defined. (Specific details are in the M16C hardware manuals.) Stop mode is exited by a hardware reset, NMI, or peripheral interrupt.

22. © 2008, Renesas Technology America, Inc., All Rights Reserved 22 Clock-Generator Mode Transitions Medium-speed mode (divided by 8 mode) High-speed, medium- speed mode PLL mode Low-speed, low-power dissipation mode Ring oscillator, ring oscillator low-power dissipation mode Wait mode Stop mode Normal mode Wait instruction Interrupt Wait instruction Interrupt Wait instruction Interrupt Wait instruction Interrupt CM10=1 Interrupt CM10=1 Interrupt CM10=1 Interrupt CM10=1 All oscillators stopped CPU operation stopped CM07=0 CM06=1 CM05=0 CM11=0 CM00=1 When low- speed mode When low-power dissipation mode Reset

24. © 2008, Renesas Technology America, Inc., All Rights Reserved 24 Voltage Detection Circuit 2.0 2.7 4.0 5.0 Vcc Voltage detection function activated by software RESET de-asserted Voltage-down interrupt RESET de-asserted RAM retention voltage flag (changes from 1 to 0) Data backup possible Warm start 0 The voltage detection circuit monitors the input voltage at the V cc1. The circuit can detect the following conditions:  Voltage down (<4.0v)  RAM retention voltage down (<2.0v) Should the voltage fall below 2.7v, a Reset signal can be generated.

25. © 2008, Renesas Technology America, Inc., All Rights Reserved 25 Course Summary Analog-to-digital converter (A/D) Digital-to-analog converter (D/A) Direct memory access controller (DMAC) CRC calculation circuit Watchdog Timer (WDT) Interrupts Clock generation circuit Voltage detection circuit