1. January 22, 1999SciFi L1 Trigger Review 1 Analog Hardware Front-end Board (CTT_FE) –Transmit (and split) the VLPC signal to the Multi-chip Modules –Discriminate the analog signals from the VLPC with the SIFT chip –Sort, buffer and Xmit the discriminated signals to the CTT_Digital –Transfer analog signal from the SIFT to the SVX2e –Digitize the analog signals with the SVX2e, an eight bit ADC for CFT fibers, 8 bits per channel for PS fibers dual, overlapped 8 bits per channel (effective 11 bits). –Supply an L3 readout for the digitized signals –Supply an L3 readout for the ADC signals –Supply the Bias voltage for the VLPC chips in each cassette and monitor the current drawn –Supply temperature monitoring for the VLPC cassette and control local heaters to trim the VLPC temperatures within the cassette

2. January 22, 1999SciFi L1 Trigger Review 2 FE Boards Need 4 FE board types –CFT/CPS Right-hand board –CFT/CPS Left-hand board –FPS/CPS Stereo Right-hand board –FPS/CPS Stereo Left-hand board Design & build 2 board types –CFT/CPS ‘Ambidextrous’ board –FPS/CPS Stereo ‘Ambidextrous’ board

3. January 22, 1999SciFi L1 Trigger Review 3 CFT/CPS FE board Used for –80 boards - CFT/CPS Axial –16 boards - FPS Forward Layer –75 boards - CFT Stereo Modified for NO charge split Cin:Apse connectors along bottom –480 CFT input channels – 32 CPS Axial channels 64 inputs after charge split Back plane connections on both ends Output to Digital boards - –480 CFT Discriminator Outputs - ‘Home’ –188 CFT Discriminator Outputs - ‘Neighbor’ – 64 CPS Discriminator Outputs - North/South & High/Low

4. January 22, 1999SciFi L1 Trigger Review 4 PS FE board Used for –16 boards - FPS Back Layer –10 boards - CPS Stereo Modified for charge split Cin:Apse connectors along bottom – 512 CPS Axial channels - to 1024 after charge split Back plane connections on both ends Output to Digital board - –512 PS Discriminator Outputs - ‘High Threshold’ –512 PS Discriminator Outputs - ‘Low Threshold’

5. January 22, 1999SciFi L1 Trigger Review 5 Front End Basic Layout

6. January 22, 1999SciFi L1 Trigger Review 6 Analog Circuit Circuit schematic for an analog FE board. This illustration shows four circuits, on the FE board the VLPC circuits are connected into groups of 64 channels. Each group has a common BIAS supply on the board and a shared trace into the cassette. the common bias supply circuit is also the common signal return. The 64 individual signal lines are also bias return lines. For charge splitting the single capacitor shown coupling the signal into the MCM is replaced with a charge division network

7. January 22, 1999SciFi L1 Trigger Review 7 PS Charge Splitting The charge from the VLPC is split 3 ways with most of the charge dumped through the drain capacitor. Minimum value of Cdrain = 25pF due to cable capacitance, Since C1 and C2 are much smaller than Cdrain the charge division is proportional to C1(2) / C1+C2+Cdrain Splitting is C d :C high :C low –CPS - (80:16:4)% :: (50:15:4)pF –FPS - (82.5:13.0:4.5)% :: (50:12:4)pF FPS forward layer split –FPS - (15:70:15)% :: (0:117:25)pF –We DON’T know how to make this work. Needs to be re-thought.

8. January 22, 1999SciFi L1 Trigger Review 8 Multi-chip Module Features 72 Inputs in two blocks of 36 Each MCM contains 4 SIFT chips and one SVX chip. The SIFT chips share common controls as two pairs. The control consists of the discriminator gain range setting threshold voltage the analog output gain range setting. SIFT channels 2 through 19 are used. The outer two channels are grounded and serve as guard channels. The SVX2e chip has 72 of 128 channels bonded. The bonded channels are for the most part every other channel.

9. January 22, 1999SciFi L1 Trigger Review 9 L3 Readout System Cartoon of the L3 Read Out. –The MCM's on each FE board are linked into two, eight SVX chips long, read out strings. –Each two strings are linked via a 50 conductor copper cable to a Sequencer board located in a crate nearby on the Platform. –The sequencer takes the data from two strings and puts it onto a single glass link and sends it to the VRB. –The VRB is read out by the VBD and into the DAQ system.

10. January 22, 1999SciFi L1 Trigger Review 10 SIFT Chip Custom chip for D0 –.8um - 3 metal HP cmos 18/20 channels individual trigger pick offs 70ns charge integration time two analog gain ranges –0.4 & 0.2 gain to SVX active matching to SVX input zero point two discriminator gain ranges

11. January 22, 1999SciFi L1 Trigger Review 11 SIFT Clocks Clock timings for the SIFT RESET Cycle –SVX is Reset –SIFT preamp is reset: PRST –SIFT discr. is reset: DRST –This readout scheme requires abort gaps in the Tevatron for reset purposes. ACQUISITION Cycles –PRST every crossing –S/H enables Dicr. output –LATCH records digital outs –S/H also samples analog –READ transfers charge All clocks are generated on FE from Crossing signal –Accuracy 5ns abs.

12. January 22, 1999SciFi L1 Trigger Review 12 Threshold Stability Discriminator reset is not needed each cycle charge input over many cycles shows no threshold drift

13. January 22, 1999SciFi L1 Trigger Review 13 Analog Transfer SIFT->SVX charge transfer is linear. The Gain selection switch provides a x2 difference. The dynamic range is more than 450 fC.

14. January 22, 1999SciFi L1 Trigger Review 14 FPS Occupancy

15. January 22, 1999SciFi L1 Trigger Review 15