1. 3/15/2002CSE 141 - Final Remarks Concluding Remarks SOAP

2. CSE 141 - Final Remarks2 Computer Technologies First Generation: Mid 40’s to late 50’s –Vacuum Tube “switches” –Acoustic or CRT memory (volatile) Second Generation: Late 50’s to mid 60’s –Individual transistors –Core memory, magnetic disks (non-volatile) Third Generation: Mid 60’s to mid 70’s –Integrated circuits (up to 1000 transistors/chip) –Complex instructions via microcode Fourth Generation: Mid 70’s and beyond –single-chip processors; semiconductor memory

3. CSE 141 - Final Remarks3 Computer Taxonomy Supercomputer Parallel or vector machine, fast memory, cost > $1 M Mainframe, Server Typically serve 100’s of users; lots of I/O power Workstation High performance; less I/O than mainframe 1-10 users, often UNIX operating system Personal Computer Single user, < $3000, often Microsoft or MAC OS. Embedded computer or controller Special-purpose interface: gameboys, microwaves,... The difference between these two is disappearing

4. CSE 141 - Final Remarks4 The computer pyramid Servers Super – computers Workstations Personal Computers There are far more lower-layer computers than higher, more powerful ones. Innovations move from top to bottom (usually). But supercomputers are being replaced by interconnected workstations & PC’s (and Playstations??). Embedded Controllers

5. CSE 141 - Final Remarks5 What is all about? 1.Layers of Abstraction –ISA’s, bus standards (e.g. PCI, Ethernet,...), Virtual Memory –Good (or popular) standards evolve and outlive individual machines E.g. IBM 360, Intel x86 2.Interfacing We’ve had to consider programming languages, compilers, operating systems, networks,... 3.Performance... this course architecture

6. CSE 141 - Final Remarks6 Memory Evolution Transistors get smaller, resulting in... DRAM chip capacity doubles every 1.5 years Transistor count doubles every 2 years Clock speed doubles every 3 years Memory speeds increase a tiny bit And then a miracle occurs... Performance doubles every 1.5 years Processor Evolution A slide from beginning of course

7. CSE 141 - Final Remarks7 Processor Architecture Program Counter LoadStore Instruction Register Control Registers ALU ALU

8. CSE 141 - Final Remarks8 pipeline the ALU Program Counter LoadStore Instruction Register Control Registers Pipe-linedALUPipe-linedALU

9. CSE 141 - Final Remarks9 separate fixed & float Program Counter LoadStore Instruction Register Control IntegerRegisters Integerpipe FloatRegistersFloatRegisters FloatingPointpipeFloatingPointpipe

10. CSE 141 - Final Remarks10 add branch predictionLoadStore Instruction Register Control + Branch Prediction Control + Branch Prediction IntegerRegisters Integerpipe FloatRegisters FloatingPointpipe Program Counter

11. CSE 141 - Final Remarks11 out-of-order execution Program Counter LoadStore Instruction Register RegisterFile Control, Branch Prediction, OutOfOrderControl, OutOfOrder IntegerRegisters + shadow registers Integerpipe FloatRegisters registers FloatingPointpipe

12. CSE 141 - Final Remarks12 more functional unitsLoadStore Instruction Register RegisterFile Control, Branch Prediction, OutOfOrder IntegerRegisters + shadow registers Integerpipe FloatRegisters registers FloatingPointpipe LoadStoreLoadStoreLoadStoreLoadStore IntegerpipeIntegerpipe FloatingPointpipeFloatingPointpipe Program Counter

13. CSE 141 - Final Remarks13 on-chip memory caches Program Counter LoadStore Instruction Register RegisterFile Control, Branch Prediction, OutOfOrder IntegerRegisters + shadow registers Integerpipe FloatRegisters registers FloatingPointpipe LoadStoreLoadStore Integerpipe FloatingPointpipe InstructionCacheInstructionCache DataCacheDataCache Level 2 Cache TLB

14. CSE 141 - Final Remarks14 Speculation What has changed? Amount of on-chip concurrency What hasn’t changed (yet)? The program counter Coming to your computer soon... Multithreaded Architectures Small changes to microprocessor: - add 3 - 7 program counters and register sets

15. CSE 141 - Final Remarks15 The Final Tuesday, March 19, 11:30 – 2:29 –Last names A – M : Center 113 (classroom) –Last names N – Z : CSB 001 (section room) You may bring: –3 pages of handwritten notes –Calculators (though I still don’t understand how they help!) –A little odorless food

16. CSE 141 - Final Remarks16 What’s on the Final ?? Entire course –Including things that weren’t on quizzes: E.g. branch hazards, superscalar scheduling Similar to quizzes: –Some easier questions, some harder –Vocabulary, details (control lines, cache operation,...), reasons for various choices, calculations. –Including a BotEE (Back of the Envelope Estimate) Note: For other problems, don’t round off answers

17. CSE 141 - Final Remarks17 Quiz 3, last question Data moves from Ethernet Controller to Memory on System Bus. –Only one pair of devices can use a bus at a time. –So, processor-memory communication is disrupted. Total amount of data moved on System Bus per image 1 MByte: Ethernet Controller to Memory 1 MByte: Memory into Cache first time (compulsory misses) 2 MByte: Extra trips of data into cache (it keeps getting kicked out) 4 MByte total Total system speed is limited by: With Fast Ethernet, getting data from cameras to Ethernet Controller With Gigabit Ethernet, the System Bus limits performance Processor and Caches Ethernet Controller Memory remote sensors Ethernet #2 System bus remote sensors Ethernet #1

18. CSE 141 - Final Remarks18 Grading Quiz 1 Hi 27.5 (out of 30) Top quartile: 21.5 Median: 18 Third Quartile: 15 Quiz 2 High 38 (out of 40) Top quartile: 34 Median: 31.5 Third quartile: 27.5 Quiz 3 Hi 28 (out of 29) Top quartile: 20 Median: 17.5 Third quartile: 15 Add 10 to Quiz 1 score Add 11 to Quiz 1 score 30 is “B” (and closer to B+ than B-)