Presentation is loading. Please wait.

Presentation is loading. Please wait.

Shantanu Dutt ECE Dept. UIC

Published byDale Rolf Patrick Modified over 9 years ago

Similar presentations

Presentation on theme: "Shantanu Dutt ECE Dept. UIC"— Presentation transcript:

1 Shantanu Dutt ECE Dept. UIC
ECE 565: VLSI Design Automation Introduction: VLSI Design Flow & Logic Opt./Tech. Mapping Shantanu Dutt ECE Dept. UIC Acknowledegements: Some slides are from publicly available slides by Naveed Sherwani (VLSI design flow) and S. Devadas (logic opt.)

2

3

4 Opt. metrics: -- Speed -- Power -- WL/area Other metrics (constraints): -- Temperature -- temperature

5 IC Design Steps (cont.) High-level Description Functional Description
Specifications Behavioral VHDL, C Structural VHDL These steps are not etched in stone: there are lots of varieties High-level description defines major components of the design and their interaction Functional description is usually at Register Transfer Level (RTL). RTL description deals with more details, lists signals, block components. Languages such as VHDL are used to describe the architecture. Figs. [©Sherwani]

6 IC Design Steps (cont.) Synthesis Physical Design Technology Mapping
High-level Description Functional Description Specifications Synthesis HLS Physical Design Technology Mapping Placed & Routed Design Logic Description Gate-level Design Again, these steps are not etched in stone: there are lots of varieties Logic description is usually generated by Computer Aided Design (CAD) tools Gate-level design (also known as “netlist”) describes the design in the atomic entities of the technology. For a CMOS design, transistors are used. In an FPGA design, look-up tables (LUTs) are used. The process of converting a logic description to a gate-level design is called technology mapping. There are a *lot* of optimizations involved after technology mapping We might go back and forth between these steps (e.g., after gate-level desc., we might simulate and find bugs => go back to RTL or high-level description and fix the bug) I haven’t shown testing/verification This course helps you understand the methods and algorithms used for automatic high-level synthesis and and physical design You will develop small CAD tools that do these steps automatically. Fabri- cation X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Packaging Figs. [©Sherwani]

7 RTL Design Flow Library/ module generators HDL RTL manual Synthesis
Includes HLS Library/ module generators HDL RTL Synthesis manual design netlist a b s q 1 d clk logic optimization Logic opt. + Technology mapping netlist a b s q 1 d clk Circuit resynthesis (e.g., buff. Ins., cell replication) physical design layout

8 Logic optimization flow
LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

9 Logic optimization flow
LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

10 Why logic optimization?
Transistor count redution AREA Circuit count redution POWER Gate count (fanout) reduction DELAY (Speed) Area reduction, power reduction and delay reduction improves design

11 Boolean Optimizations
Involves: Finding common subexpressions. Substituting one expression into another. Factoring single functions. Find common expressions Extract and substitute common expression f1 = AB + AC + AD + AE + A B C D E ì F = í î f2 = A B + A C + A D + A F + A B C D F f1 = A ( B + C + D + E ) + A B C D E ì F = í î f2 = A ( B + C + D + F ) + A B C D F g1 = B + C + D ì G = í f1 = A ( g1 + E ) + A E g1 ï î f2 = A ( g1 + F ) + A F g1

12 Algebraic Optimizations
Algebraic techniques view equations as polynomials Rules of polynomial algebra are used For e.g. in algebraic substitution (or division) if a function f = f(a, b, c) is divided by g = g(a, b), a and b will not appear in f / g Boolean algebra rules are not applied

13 Logic optimization flow
LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

14 Standard cell library For each cell (e.g., NANDs, NORs, Invs, AOIs)
Functional information Timing information Input slew Intrinsic delay Output capacitance Physical footprint Power characteristics

15 Sample Library INVERTER 2 NAND2 3 NAND3 4 NAND4 5

16 Sample Library - 2 AOI AOI

17 Mapping via DAG* Covering
Represent network in canonical form Þ subject DAG Represent each library gate with canonical forms for the logic function Þ primitive DAGs Each primitive DAG has a cost Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs * Directed Acyclic Graph

18 Trivial Covering Reduce netlist into ND2 gates → subject DAG
7 NAND2 = 21 5 INV = 10 31 (area cost)

19 Covering #1 2 INV = 4 2 NAND2 = 6 1 NAND3 = 4 1 NAND4 = 5
19 (area cost)

20 Covering #2 1 INV = 2 1 NAND2 = 3 2 NAND3 = 8 1 AOI21 = 4
17 (area cost)

21 Multiple fan-out

22 Partitioning a Graph Partition input netlist into a forest of trees
Solve each tree optimally Stitch trees back together

23 Optimum Tree Covering INV 11 + 2 = 13 AOI21 4 + 3 = 7 NAND2
= 11 NAND2 3 + 3 = 6 INV 2 NAND2 3 NAND2 3

24 DAG Covering steps Partition DAG into a forest of trees
Normalize the netlist Optimally cover each tree Generate all candidate matches Find optimal match using dynamic programming

25 For more details on logic opt. …
Refer to Srinivas Devadas’ slides for 6.373

Download ppt "Shantanu Dutt ECE Dept. UIC"

Similar presentations

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.
TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.

TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.
Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.

Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.
ECE 667 - Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)

ECE Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

ELEC Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.
ECE 551 Digital System Design & Synthesis Lecture 08 The Synthesis Process Constraints and Design Rules High-Level Synthesis Options.

ECE 551 Digital System Design & Synthesis Lecture 08 The Synthesis Process Constraints and Design Rules High-Level Synthesis Options.
Logic Synthesis – 3 Optimization Ahmed Hemani Sources: Synopsys Documentation.

Logic Synthesis – 3 Optimization Ahmed Hemani Sources: Synopsys Documentation.
CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification.

CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification.
ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems
The Design Process Outline Goal Reading Design Domain Design Flow

The Design Process Outline Goal Reading Design Domain Design Flow
ELEN 468 Lecture 121 ELEN 468 Advanced Logic Design Lecture 12 Synthesis of Combinational Logic I.

ELEN 468 Lecture 121 ELEN 468 Advanced Logic Design Lecture 12 Synthesis of Combinational Logic I.
Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.
CSE241 L5 Synthesis.1Kahng & Cichy, UCSD ©2003 CSE241 VLSI Digital Circuits UC San Diego Winter 2003 Lecture 05: Logic Synthesis Cho Moon Cadence Design.

CSE241 L5 Synthesis.1Kahng & Cichy, UCSD ©2003 CSE241 VLSI Digital Circuits UC San Diego Winter 2003 Lecture 05: Logic Synthesis Cho Moon Cadence Design.
Technology Mapping.

Technology Mapping.
EDA (CS286.5b) Day 2 Covering. Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique.

EDA (CS286.5b) Day 2 Covering. Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique.
VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.

VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.
Logical Effort.

Logical Effort.
Penn ESE535 Spring2008 -- DeHon 1 ESE535: Electronic Design Automation Day 2: January 23, 2008 Covering.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 2: January 23, 2008 Covering.
1 Technology Mapping as a Binate Covering Problem Slides adapted from A. Kuehlmann, UC Berkeley 2003.

1 Technology Mapping as a Binate Covering Problem Slides adapted from A. Kuehlmann, UC Berkeley 2003.
Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.

Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.

Similar presentations

Ads by Google