1. Unit - II
The ARM processor

2. Beagle Bone : Beagle Board Beagle BoardxM Beagle Bone White
Beagle Bone Black
Based on ARM cortex A8
512 DDR3 RAM
4 GB on board Storage

3. Introduction to Beagle Boards :
Beagle boards are tiny computers with all the capabilities of today’s desktop machine.
To teach open source hardware and software capabilities
Produced by Texas Instruments in association with Digi-Key and Newark element14
Developed as a demonstration of OMAP (Open Multimedia Application platform) System on Chip (Soc)
CPU: ARM Cortex A8
Supported OS: Linux, Minix, FreeBSD, Android, Symbian, RISC OS

4. Beagleboard – Rev. C

5. Hardware - Beagleboard
OMAP3530 (Soc) forms the core of the board.
Uses Package on Package stacking of memory on top of OMAP
Memory:
256MB NAND, 256MB DDR SDRAM
Interfaces:
DVI-D (via HDMI connector), JTAG, RS232, USB2 OTG
Stereo In, Stereo Out, S-Video, USB2 Host
Expansion Header: I2C, I2S, SPI, MMC/SD
Can be USB bus powered or take DC power

6. Using the Beagleboard Booting:
NAND -> USB-> UART -> MMC (For Beagle Board)
USB -> UART -> MMC -> NAND (For processor)
Uses U-Boot (Universal Boot loader)
Provides a simple Command Line Interface to manipulate hardware prior to booting a kernel
MMC/SD is the only way to bring up a new board.

7. Beagleboard - Software
Distributions you can use:
Angstrom
Ubuntu
Android (Google’s open source software stack for mobile devices)
Number of other embedded Linux distros.

8. Developing for Beagleboard
Openembedded (OE):
Provides an easy to use build environment
Collection of metadata about software packages
support for many hardware architectures
runs on any Linux distribution
Cross Compilation
Other options:
Use the Android SDK
Build your own toolchain
Start from a ready made image

9. BeagleBone Announced in the end of October 2011
The BeagleBone is a barebone development board with a Sitara ARM Cortex-A8 processor
720 MHz, 256 MB of RAM
Two 46-pin expansion connectors
On-chip Ethernet
A microSD slot and a USB host port
A device port which includes low-level serial control and JTAG hardware debug connections, so no JTAG emulator is required.

10. BeagleBone Features : Built-in networking Remote access File system
Use many different programming languages
Multitasking
Linux software
Open Source

11. BeagleBone Black

12. Component Locations

13. Connector and switch Locations

14. 4 LEDs

15. Lets start with basic: LEDS
There are four user LED(s) on the Beaglebone. The user LED(s) are
Accessible from user space on the file system at this location:
/sys/class/leds/
There is one directory per user LED, named as shown below:
/sys/class/leds/beaglebone::usr0/ (GPIO1_21)
/sys/class/leds/beaglebone::usr1/ (GPIO2_22)
/sys/class/leds/beaglebone::usr2/ (GPIO2_23)
/sys/class/leds/beaglebone::usr3/ (GPIO2_24)

16. On-board LED:
Write the following commands in your terminal (First one is for turning ON and latter for OFF):
USER0 : heartbeat indicator from the Linux kernel.
USER1 : SD card access
USER2 : activity indicator. Turns on when the kernel is not in the idle loop.
USER3 : Onboard eMMC is access.

17. Comparison :

18. U-Boot : Universal Boot loader for embedded systems
Locating and loading the kernel with the set arguments
Setting up the arguments
Initializing additional hardware
Makes booting from serial and USB port possible

19. Boot Modes : eMMC Boot (MMC1) SD Boot (MMC0) Serial Boot
Uses onboard memory
Default boot mode
Fastest
SD Boot (MMC0)
uSD card
Serial Boot
Boots from serial ports
USB Boot (USB0)
Boots from USB

20. Booting Options : Without holding the boot button :
eMMC Boot
uSD Boot
Serial Boot
USB Boot
Holding the boot button :

21. BBB interfacing : Initialization Input Logic Output Export Direction
Changing the values
Output

22. BBB interfacing with Stepper Motor
Connector Number
BBB PIN
Number
PIN Description
PIN connects to stepper motor connected FRC
Function P9
1,2
GND
GND(25pin) 5
VCC(5V)
VCC(26pin)
VCC 11
GPIO0[30]
FRC-21pin
Out 12
GPIO1[28]
FRC-22pin 13
GPIO0[31]
FRC-19pin 14
GPIO1[18]
FRC-20pin

23. Embedded System Processors
A number of choice available for embedded processors
Two categories are:
Standalone Processors
Requires external chipset to form complete system
Integrated Processors
SoC: System on Chip

24. Standalone Processors
Dedicated exclusively to the processor functions
Needs external controllers to interfacing with surroundings. E.g. DRAM controller, keyboard controller and serial ports
Highest Overall CPU performance.

25. Standalone Microprocessor Based System

26. Standalone Processors: Example
Many standalone processors in 32 bit and 64 bit exist and widely used in embedded systems:
IBM 970FX :
A high performing 64 bit capable stand alone processor.
Superscalar architecture: Core can fetch, decode and execute for more than one instruction at a time (Deeply Pipelined)
Used also in IBM blade server platform

27. Standalone Processors: Example
Intel Pentium M
One of the most popular x86 architecture for 32 and 64 bit.
Super scalar architecture like IBM 970 FX.
Used in many earlier laptops and commercial embedded systems
Intel Atom
Widely used in notebooks and embedded system applications. Known for low power consumption

28. Integrated Processor :SoC

29. SoC A microchip that has all the components to run the system.
Integrates all the components of computer in a single chip
Majority of embedded application uses Integrated processors (SoC)
Beagleboard
Processor TI OMAP3530 SoC - 720 MHz ARM Cortex-A8 core

30. ARM TIMELINE :
1985: Acorn Computer Group manufactures the first commercial RISC microprocessor. (ARM – I V)
1990: Acorn, Apple and VLSI based Technology group = Advanced RISC Machines (A.R.M.).
1991: ARM6, First embeddable RISC microprocessor.
1993 : ARM7, the first multimedia microprocessor is introduced.
Users :
Samsung
Atmel
Philips
Etc.

31. ARM :

32. Advanced RISC Machine :
Instructions are same size : 32 bit
Instructions are executed in 1 cycle
Load/Store access memory
Advantage:
Number of transistors are less compared to similar CISC architecture.
Less hardware results in less die size
Low power consumption

34. Advanced Features Thumb: MMU and MPU:
A new 16 bit instruction set called thumb is made available.
This is less powerful instruction set but quite useful for application that do not require full power of 32 bit instructions.
Advantage: High Code Density
(Higher amount of code in per unit memory area)
MMU and MPU:
Desktop system requires it.
It depends on application requirement in embedded system
ARM processor can be implemented with MMU and MPU or with one of them or neither of them.

35. Advanced Features Debug Interface:
There is chip testing unit called JTAG (joint testing action group) interface.
JTAG standard defines a set of interface for testing hardware and initial code.
Jazalle DBX: (Direct Byte code Execution)
Some ARM processors have direct execution support for byte code in hardware.
Useful in devices for execution games and java application that otherwise require a heavy JVM.

36. Advanced Features Vector Floating Point Unit Cache:
Hardware support for floating point computation
Cache:
The first ARM processor with Cache is ARM3. It had 1 KB chip of 4 KB.
ARM 7 had a cache of 8 KB.

37. Advanced Features Fast Multiplier Synthesizable:
Even though ARM is a RISC processor, there are many features that do not conform to RISC philosophy
ARM processors may have a fast multiplier hardware unit.
Synthesizable:
Design Code (RTL) is available with License, using which extensions and modification are possible in basic core

38. Advanced Features Embedded ICE (In Circuit Emulator) Macrocell:
The current hardware trend is to design system as macrocells.
The ARM core could be considered as macrocell and other units may also be added as (e.g. peripheral units) macrocells.
Some processor has embedded ICE macrocell for testing.
Used for debugging and have registers to set watch points and breakpoints .

39. Naming Conventions for ARM
Example: ARM7TDMI

43. ARM CORTEX Latest in ARM is cortex series
Based on architecture V7 version:
THUMB-2 technology (Both 16 and 32 bit supported)
No need to switch between ARM and THUMB instruction set
Cortex has well defined profile for different application areas: A R M

44. Cortex Profiles A profile:
For High End applications in Embedded Systems with modern OS. (e.g. Android)
ARMv7-A architecture
Used in Mobile phones and Video Systems
R Profile:
For high end application on systems with Real time capabilities
ARMv7-R architecture
Used in safety critical systems
M profile:
Designed for Core embedded microcontroller type systems
ARMv7-M architecture
Used in control applications

46. Advanced Features : Data bus width : Computational capability:
32 bit data bus
32 bit read/write in 1 cycle
Computational capability:
RISC Approach provides good computations
RISC architecture with few CISC add-ons
Low Power:
Power saving
Operates at low clock frequencies
60MHz to 1 GHz

47. Advanced Features : Multiple Register Instructions : DSP Enhancement:
Data processing with registers mostly
Processing instructions do not use addressing modes that uses one operand in memory.
But, instructions for loading and storing data to registers.
DSP Enhancement:
Additional DSP features

48. Pipelining : Dividing instruction processing in sub-stages
3 Stage pipeline: (ARM-7)
Fetch – Decode – Execute
5 Stage Pipeline: (ARM-9)
Fetch – Decode – Execute – Buffer - Write
(ARM-10) – 6 stage pipeline
Drawback:
Problem with branch instructions
Due to sequence change some instructions are discarded
Loss of data, computation time
Higher penalty with more stages

50. Instruction Set Architecture
Programmers view of computer architecture
Consists of :
Instruction Sets
Addressing Modes
Registers etc.
Basic ISA of all ARM processor are more or less same

56. CPSR (Current Program Status Register)
Bit Nos.
Notion
Interpretation
0 to 4
Mode
Specifies the current mode of operation 5 T
State : ARM = 1 or THUMB = 0 6 F
Disables (F=1) FIQ 7 I
Disables (I=1) IRQ
8 to 23
Undefined
25 to 26 24 J
J=1 means in Jazalle state 27 Q
Sticky Overflow flag
28 to 31
V C Z N
Condition flags

57. CPSR
N: Negative (N=1 indicates negative results) Z: Zero ( Z=1 indicates result is 0) C: Carry V: Overflow

59. Exception Priorities :
Reset (Highest)
Data abort
FIQ
IRQ
Prefetch abort
SWI, undefined instruction (Lowest)

61. Data Type 6 data types in all:
Signed and unsigned
32 bit/ 16 bit and 8 bit operations supported
Processing tool offers the option of storing data in little endian and big endian formats
Data Alignment:
For word (32-bit) should have least 2 bits of address as 0
Eg: 0x1200
For unaligned data like 0X1201
(32 – bit ) will access 2 memory cycles 0x12001, 0x1204

62. Assembly Language Rules :
Label
Opcode / Instruction field
Operand field
Comment
Label ADD R1,R2,R3 ;Add instruction

64. Shift and Rotate Two types of shifts are possible
Logical and Arithmetic
LSL (Logical Shift Left):
For a 32 bit register, shift left (a specified number of times) results in shifting every bit left and vacant bits at right are filled with zeroes
The last bit shifted out from the left is copied to the carry flag
Left shift by one bit position corresponds to multiplication by 2.
An LSL of 5 implies multiplication by 32

65. Shift and Rotate LSR (Logical Shift Right)
Similar to LSL but shifts bits in right
Vacant bits at left filled by zeroes.
The last bit shifted out is retained in carry flag
Shifting right by 1 bit is equivalent to dividing the number by 2.
Two right shift cause a division by 4

66. Shift and Rotate ASR (Arithmetic Shift Right):
Vacant bit in the left is filled with MSB of the original number.
This type of shift has the function of doing ‘sign extension’ of data
There is not instruction for Arithmetic Shift Left

67. Shift and Rotate ROR (Rotate Right) Data is shifted right
The bit shifted out from right is inserted back through left.
The last bit rotated out is available in carry flag.
There is no Rotate Left instruction, because left rotate ‘n’ times can be achieved by rotating right ‘32-n’ times.
For example rotating 4 times to the left is achieved by rotating 32-4 = 28 times to the right

68. Shift and Rotate RRX (Rotate Right Extended):
This corresponds to rotating right though the carry bit.
Bits dropped off from the right side is moved to CF and the carry bit enters through the left of the data.

70. Format of Shift and Rotate Instruction
The number of bit position by which shift or rotate operation need to be done is specified by a constant or another register.
Example:
LSL R2,#4 ; shift left logically the content of R2 by 4 bit position
ASR R5,#8 ; Shift right arithmetically the content of R5 by 8 bit position
ROR R1, R2 ;Rotate the content of R1 by the number specified by R2

71. Problem The content of some of the registers are given as:
R1=0xEF00DE12
R2=0x F
R5=4
R6=28
Find the result in destination register for following:
LSL R1, #8
ASR R1, R5
ROR R2, R6
LSR R2, #5

72. Solution Find the result in destination register for following:
R1=0xEF00DE12
R2=0x F
R5=4
R6=28
Find the result in destination register for following:
LSL R1, #8 (Ans: 0x00DE1200)
ASR R1, R5 (Ans: 0xFEF00DE1)
ROR R2, R6 (Ans: 0x456123F0)
LSR R2, #5 (Ans: 0x0022B091)

73. Combining the operation of Move and Shift
MOV R1, R2, LSL #2
MOV R1, R2, LSR R3
In both ,instruction R1 is the destination register.
In first instruction, the source operand i.e. content of R2 is logically shifted left twice and then moved to R1.
In second instruction, amount of shifting is specified by R3.

74. Problem R5= 0x72340200 and R2=4 Find MOV R3, R5, LSL #3
MOV R6, R5, ASR R2

75. Problem
R5= 0x and R2=4
Find
MOV R3, R5, LSL #3 (R3=0x91A01000)
MOV R6, R5, ASR R2 (R6=0x )

76. Conditional Execution
An important and distinguished feature of ARM
Instruction is executed only if specified condition is true.
In general, all data processing instruction are expected to affect conditional flags.
But in ARM, we must suffix the instruction with ‘S’ for this to happen.
‘S’ suffix in data processing instruction causes the flags in CPSR to be updated.

77. Example MOV R3, R5, LSL #3 MOVS R3,R5, LSL #3
No affect on carry flat and N flag in CPSR
MOVS R3,R5, LSL #3
The MOV instruction is made conditional by suffixing it with S.
C and N flags are now set.
This flag setting can be used to make an instruction following it to be conditional.

78. Recap: Carry Flag
The carry (C) flag is set when an operation results in a carry, or when a subtraction results in no borrow.
In ARM, C is set in one of the following ways:
For an addition, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise.
For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.
For non-additions/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.
For other non-additions/subtractions, C is normally left unchanged.

80. Detailed Format :

81. Detailed Format :

84. Question : What will be the result : ADD R1, R2, R2, LSL #3
RSB R3, R3, R3, LSL #3
RSB R3, R2, R2, LSL #4
SUB R0, R0, R0, LSL #2
RSB R2, R1, #0

85. Solution : What will be the result :
ADD R1, R2, R2, LSL #3 R1 = R2 + 8 R2
RSB R3, R3, R3, LSL #3 R3 = 8R3 – R3
RSB R3, R2, R2, LSL #4 R3 = 16R2 – R2
SUB R0, R0, R0, LSL #2 R0 = R0 – 4R0
RSB R2, R1, #0 R2 = 0 – R1

86. Q. Write a small assembly program for ARM, required that 2 numbers stored in
R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal
Put it in R9.

87. Q. Write a small assembly program for ARM, required that 2 numbers stored in
R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal
Put it in R9.
SUBS R3, R1, R2 ;R3 = R1 – R2
MOVEQ R9, R1 ;IF R1=R2 / Z= R1 -> R9
MOVHI R10, R1 ;IF R1 > R2 / C= R1 -> R10
;MOV R10, R2
;MOVLS R10,R2 ;if R1<=R2 , C=0|Z=1 ,
move R2 to R10

89. Flag setting after compare InstructionIf C Z
R3>R4 1
R3<R4
R3=R4

90. TST Instruction
TST is similar to compare, but it does ANDing and then sets conditional flags.
If the result of ANDing is zero, then zero flag is set.
It can be used to verify at least one of the bits of a data word is set or not.
Write instruction to verify the LSB of a word in register R1 is set or not.
TST R1, #01

91. TEQ Instruction TEQ does exclusive ORing which tests for equality.
If both operands are equal then only zero flag is set.
TEQ R1,#45

92. Data Processing Instructions :

93. Multiplication :

94. Example : MUL R1,R2,R3 MULS R1,R2,R3 MULSEQ R1,R2,R3 MULEQ R1,R2,R3
UMULL R1, R2, R3, R4

95. Branch Instructions : B Branch BL Branch and Link
BX Branch and Exchange
BLX Branch and Exchange with Link
Eg :
<Label> B New
STOP B STOP
<Label> BNE New
<Label> BHI New

96. Assembly Programming in ARM
Two kind of statements :
Executable statements
Directives (related to assembler)
AREA
ENTRY RN
END
Defining data

97. Directives : ENTRY END AREA
Entry point of first executable instruction
END
AREA
AREA <NAME_OF_REGEION> , CODE/DATA, READONLY/READWRITE
Eg. AREA SORT,CODE,READONLY

98. Directives : Defining Data RN EQU NUMS DCB 9, 10, 15
NUM1 DCW 0x6787, 0x4565
NUM2 DCD 0x , 0x RN
Giving variable names to registers
X RN 1
Y RN 10
EQU
Equate
FACT EQU 35
ASD EQU 0x

99. Question : Write a program to find 3X + 4Y + 9Z , WHERE X = 2 Y = 3

101. Program to calculate factorial of 5 numbers
Write down an ARM assembly program to calculate factorial of 5.
Instructions Involved:
MUL
SUBS
BNE

102. Solution
AREA FACTO, CODE ;Define the code area ENTRY ;entry point MOV R1, #5 ;R1=5 MOV R2,#1 ;R2=1 REPT MUL R2, R2, R1 ;R2=R2XR1 SUBS R1, R1, #1 ;R1=R1-1 BNE REPT ;Branch to REPT if Z!=0 B B STOP ;last line END ;End

103. Subroutine/Procedures
Another kind of branch used in Subroutine calls – BL (Branch and Link)
When a BL encountered (control transfer to new sequence of instruction OR the new procedure) ARM saves current PC value in Link register.
PC then starts with new instruction set (Branch Target).
At the end of procedure , LR is copied to PC

104. Finding 3X2 + 5Y2 , where X=8 and Y=5
AREA PROCED, CODE
ENTRY
MOV R2, #8
BL SQUARE
ADD R1,R3,R3 , LSL #1
MOV R2, #5
ADD R0,R3,R3,LSL #2
ADD R4, R1, R0
STOP B STOP
SQAURE MUL R3, R2, R2
MOV PC,LR
END

107. Example
The constant value being added to Rn is immed_8 rotated right by 2*rotate_imm.

108. Constants :
Only decimal values within range 0 – can be created using this schema.
Instructions MOV, MVN can also be used with ROR

109. Literal Pools
Literal Pool is a lookup table used to hold literals during assembly and execution.
Literals : Written exactly as it is meant to be interpreted. Example: x=125 ; x is variable, 125 is literal
Take an example of immediate operand
MOV R1, #0x
Assembler will give error that such constants cannot be generated.
To avoid the situation we can write:
LDR R1, = 0x
(This is a pseudo instruction for assembler)

110. Literal Pools
LDR R1, =0x
The pseudo instruction forces the assembler to check for one of the following possibilities
Can the constant be constructed with MOV or MVN combined with rotation?
Assembler places the value in literal pool and generated and LDR with program relative address
Memory Space after END
LTORG statement

112. Example LDR R3,[R2, LSL #2] STR R9, [R1,R2, ROR #2] LDR R4,[R3,R2]
The effective address is the content of R2 left shifted by 2 (multiplied by 4)
STR R9, [R1,R2, ROR #2]
The effective address is specified by R1 and R2 and a right rotation
LDR R4,[R3,R2]
The effective address here is sum of R3 and R2
STR R5,[R4, R3, ASL #4]
The effective address is the sum of content of R4 and the arithmetically left shifted (by 4) content of R3

113. Bytes, Half Words and Words
ARM has instruction to transfer specifically a word (32 bits), half word (16 bits) or a byte 8 bits) between memory and registers.
Load Instruction
Description
Store Instruction
LDR
Load Word
STR
Store Word
LDRH
Load Half Word
STRH
Store Half Word
LDRSH
Load Signed Half Word
LDRB
Load Byte
STRB
Store Byte
Load Signed Byte

114. Problem Memory areas are referenced by two registers
R1=0x , R2=0x
LDR R3,[R1]
LDRB R3,[R1]
LDRH R3, [R1]
STRB R3,[R2], provided that R3= 0x
Address
Byte Stored 0X 56 0X 23 0X 0D 0X AE

115. Solution: LDR R3,[R1] LDRB R3,[R1] LDRH R3, [R1]
R3 = 0xAE0D2356
LDRB R3,[R1]
R3 = 0x
LDRH R3, [R1]
R3 = 0x
STR R3,[R2], provided that R3= 0x AE0D2356
Address
Byte Stored 0X 56 0X 23 0X 0D 0X AE
STRB
STRH

116. Loading Signed Numbers :
R7 = 0xCDEF8204
LDR R1, [R7] R1 = 0xCDEF8204
LDRSH R1, [R7] R1 = 0xFFFF8204
LDRSB R1, [R7] R1 = 0x

117. Indexed Addressing Modes
Pre Indexed Addressing Modes
LDR R0, [R7,#4]
R7 is the base register and effective address is R7+4 . The data at effective address is copied to R0.
Add ! For write back option
LDR R0, [R7,#4]! R7 = R7 + 4;
Post Indexed Addressing Mode
LDR R0, [R4],#4
The data pointed by R4 is first copied to R0. Then the content of R4 is changed to R4+4

118. Multiple Load and Store (LDM and STM)
Multiple register load means that multiple memory locations are to be accessed and loaded into multiple registers.
There is a base register acting as pointer to the first memory location to be accessed.
The register then incremented or decremented to point the next memory location
LDM/STM{condition} address-mode Rn {!} , reg-list

119. LDM and STM Suffixes used with LDM and STM IA : Increment After
IB : Increment Before
DA : Decrement After
DF : Decrement Before
LDMDA R0,{R4-R9}
32 bit word pointed by R0 is copied to R4
32 bit word pointed by R0-4 is copied to R5
32 bit word pointed by R0-8 is copied to R6
and so on till R9.

120. LDMIA R10,{R9, R1-R3}
32 bit word pointed by R10 is copied to R1
32 bit word pointed by R10+4 is copied to R2
32 bit word pointed by R10+8 is copied to R3
32 bit word pointed by R10+12 is copied to R9

121. The STM instruction Same format as LDM STMIA R1, {R2-R4}
Equivalent to the following instruction
SRT R2, [R1]
STR R3, [R1,#4]
STR R4, [R1,#8]

124. ARM9: Major Improvements over ARM7
Decreased heat production and lower overheating risk.
Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process.
Cycle count improvements. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores.
Some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

125. ARM 9
Implement Harvard Architecture: The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.

128. ARM9: LPC 29XX ARM MCU The LPC29xx consists of:
An ARM968E-S processor with real-time emulation support
An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers
Two DTL buses for interfacing to the interrupt controller
Three or four ARM Peripheral Buses (APB) for connection to on-chip peripherals

129. ARM9 : Advanced Microprocessor Bus Architecture
The ARM’s AMBA protocols are an open standard, on-chip interconnect specification.
It specifies the connection and management of functional blocks in a System-on-Chip (SoC).
It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

130. ARM9 : AHB and APB AHB stands for Advanced High-performance Bus
APB sands for Advanced (sometimes ARM) Peripheral Bus.
Both are part of the Advanced Microprocessor Bus Architecture (AMBA).
Dedicated AHB to APB bridges are used to interconnect.

132. ARM Cortex M3 Cortex-M3 Processor
The ARM Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications
 Specifically developed to enable partners to develop high-performance low-cost platforms for:
Microcontrollers
automotive body systems
Industrial control systems
wireless networking and sensors
LPC17XX