1. ITRS ERD July 20081 Hybrid CMOS / Nanoelectronic Circuits (CMOL, FPNI, 3D CMOL, etc.) Hybrid CMOS / Nanoelectronic Circuits (CMOL, FPNI, 3D CMOL, etc.) Konstantin K. Likharev Stony Brook University Acknowledgments: - useful discussions: P. Adams, P. Allen, J. Barhen, S. Das, A. DeHon, P. Franzon, D. Hammerstrom, R. Karri, R. Kiehl, P. Kuekes, J. H. Lee, J. Li, X. Liu, J. Lukens, X. Ma, A. Mayr, C. A. Moritz, V. Patel, D. Resnick, N. Simonian, G. Snider, S. V. Sreenivasan, M. Stan, D. Stewart, D. Strukov, Z. Tan, W. Wang, R. Waser, R. S. Williams, T. Zhang - financial support: AFOSR, DOD, FCRP (via FENA Center), NSF Literature: see the White Paper; more online: rsfq1.physics.sunysb.edu/~likharev/nano/rsfq1.physics.sunysb.edu/~likharev/nano/

2. ITRS ERD July 20082 CMOS/NANO HYBRIDS: THE IDEA bottom nanowire level top nanowire level similar two-terminal nanodevices at each crosspoint Historic (first?) version: (J. Heath, P. Kuekes, G. Snider, R. S. Williams 1998) Basic current version: V I ON state 0 +Vt+Vt OFF state V+V+ V-V- -Vt-Vt

3. ITRS ERD July 20083 RELATION TO DEVICE TECHNOLOGIES DISCUSSED TODAY Nanoscale Devices Applicability to CMOL/FPNI NEMS switches 2-terminal switches OK Spin torque transfer devices STT junctions may be OK Carbon-based devices n/a Atomic / electrochemical metal switches OK Collective spin devices n/a Single electron devices latching switch OK ___________________________________________________________ + Phase-change cells + Organic layers (with and w/o embedded clusters)

4. ITRS ERD July 20084 BISTABLE TWO-TERMINAL DEVICES (a.k.a. latching switches, a.k.a. programmable diodes) DC I-V curve (schematically): Several material options demonstrated: - polymers (with or w/o clusters) - metal oxides (or sulfides) - solid electrolytes - amorphous silicon - chalcogenides - molecular SAMs V I state 1 0  1 1  0 0 +Vt+Vt state 0 V+V+ V-V- -Vt-Vt A few examples: Y.-S. Lai et al. (2005) Poly(N-vinylcarbazole) L. Bolzano et al. (2004) Aluminum tris(8-hydroquinoline) R. T. Weitz et al. (2006) Copper-2,3-dichloro-5,6- dicyano-p-benzoquinone

5. ITRS ERD July 20085 METAL-OXIDE LATCHING SWITCHES “Memory effects” in oxides have been known for a while: G. Dearnaley et al., Rev. Prog. Phys. (1970): a review with 150+ references Just a few recent references: metal: S. Seo et al., APL (2003)Ni B. J. Choi et al., JAP (2005)Ti H. Sim et al., Microel. Eng. (2005)Nb D. Lee et al., EDL (2005)Zr A. Chen et al., IEDM’05Cu M. Kund et al., IEDM’05Ag D. C. Kim et al., APL (2006)Nb N. Banno et al., IEICE TE (2006)Cu(S) T.-N. Fang et al., ICMTD’07Cu L. Courtade et al., ICMTD’07Ni W. Guan et al., APL (2007)Zr S.-W. Kim & Y. Nishi, NVMTS’07Cu(S) D. Stewart, NVMTS’07Ti K.-C. Liu et al., NVMTS’07Hf D. Lee et al., APL (2007)Mo ONOFF With time, data are becoming more reproducible: A. Chen et al. (IEDM’05) Just a few examples: B. J. Choi et al. (2005)D. Lee et al. (2007)A. Chen et al. (2005) Cu Cu 2 O TE

6. ITRS ERD July 20086 RECENT RESULTS: Si /α-Si / M JUNCTIONS Y. Dong et al., 2008S. H. Jo and W. Lu, 2008

7. ITRS ERD July 20087 NANOWIRE CROSSBARS crossbar with F nano = 15 nm J. Green et al. (2007) [Caltech + UCLA] G.-Y. Jung et al. (2006) [HPL + Caltech] W. Wu et al. (2005) [HPL]

8. ITRS ERD July 20088 ADVANCED LITHORGAPHIES crossbar with F nano = 15 nm J. Green et al. (2007) www.zeiss.com IMPRIO 1100 from Molecular Imprints, Inc. (“sub-50nm”) Nanoimprint EUV ILBlock-copolymer B. Wua and A. Kumar (2007) www.almaden.ibm.com

9. ITRS ERD July 20089 “CMOL” INTERFACE CONCEPT (I) CMOS stack (just a cartoon) interface pins gold nanowire levels (nanoimprint) MOSFET nanodevices (latching switches) interface via (“pin”) Si wafer K. L. (2004)

10. ITRS ERD July 200810 Tip radii 2-10 nm http://www.oxfordplasma.de/ process/sibo_wtc.htm http://my.ece.ucsb.edu/mishra/ vacuummicroelec/progressb.0157.htm SILICON PIN ARRAYS (developed mostly for field emission) Main challenge: Move to the back end of the CMOS process flow (metals?)

11. ITRS ERD July 200811 (a) (b) (c) (d) (e) (f) POSSIBLE CMOL FABRICATION FLOW K. L. (2007a)

12. ITRS ERD July 200812 CMOL INTERFACE CONCEPT (II) Most important feature: pin array tilt by angle  = arcsin(F nano /  F CMOS ) = arctan(1/r) Every nanowire (and hence every crosspoint) may be addressed from CMOS! 2  F CMOS pin 2A 2F nano  pin 1 pin 2B 2rF nano K. L. (2004, 2005); D. Strukov and K. L. (2006) A B

13. ITRS ERD July 200813 CMOL: YIELD WITHOUT ALIGNMENT Shift along the top level: fine fine bad? bad! fine fine Shift along the bottom level: fine fine bad! fine fine fine Theoretical yield maximum: 100% K. L. (2007)

14. ITRS ERD July 200814 RESISTIVE MEMORIES: ARCHITECTURE D. Strukov and K. L. (2007a) cell addresses block row address data I/O block address decoder ECC unit block select decoder data I/O external address memory cell array select decoder address control mapping table data decoder A col1 A col2 A row2 A row1 data A row2 select A row1 select data A col1 R pd Top-level structure: Limited data granularity: CMOS cell: CMOL block: Barrel shift decoder:

15. ITRS ERD July 200815 RESISTIVE MEMORIES: EVALUATION RESULTS D. Strukov and K. L. (2007a) Bottom line: - density up to 1 Tb/cm 2 feasible (see below) - speed, power OK - defect tolerance acceptable (~10%) Final results example: density and defect tolerance  10 buffer sense amplifier Equivalent circuit for readout delay calculation: Total chip area optimization:

16. ITRS ERD July 200816 RECONFIGURABLE LOGIC CIRCUITS Generic CMOL fabric D. Strukov and K.L. (2005) (b) output nanowire input nanowire CMOS column 2 CMOS row 1 CMOS inverter CMOS row 2 V DD B A F F A B CMOS inverter nanodevices pass transistor ABAB F (c) R ON R pass C wire CMOS column 1

17. ITRS ERD July 200817 CMOL FPGA CIRCUIT: EXAMPLE D. Strukov and K.L. (2005) 0 aiai bibi (g i 0, p i 0 ) (g i l, p i l )(g j l, p j l ) (g i l+1, p i l+1 ) (g i l, p i l ) p i 0 cici sisi gilgil c i =g i l+1 31 INPUT OUTPUT 32-bit Kogge-Stone adder… (a)(a) (b)(b) a0a0 b0b0 a1a1 b1b1 a 30 b30b30 a 31 b31b31 s0s0 s1s1 s 30 s 31 …mapped on the CMOL fabric… …before… …and after reconfiguration (@ 50% of bad devices)

18. ITRS ERD July 200818 CMOL FPGA: RESULTS (I) defect tolerance....and performance D. Strukov and K.L. (2005) Bottom line: yield >99% for 22-25% (!) of bad devices F CMOS = 45 nm 32 nm 22 nm F CMOS = 32 nm, F nano = 9 nm: A  110  m 2,   0.9 ns CMOS FPGA with the same F CMOS : A  70,000  m 2,   1.7 ns

19. ITRS ERD July 200819 CMOL FPGA CAD 1.0 D. Strukov and K.L. (2006a) Design flow: First goal: Toronto 20 benchmark circuit set Latched CMOL fabric: tile boundary latch cellbasic cell 2F nano 2 a F nano  SIS: Technology (NOR gate and latch) mapping Input circuit blif format Initial value of N Heuristic placement Global router Exit with success Increase N count max < T-N -∆ count max > T-N N = 0 Circuit pre- processing Defective cells Decrease N otherwise Exit without success in out CMOS latch 4  F CMOS Latch cell:

20. ITRS ERD July 200820 CircuitCMOS FPGA (F CMOS = 45 nm)CMOL FPGA (F CMOS = 45 nm, F nano = 4.5 nm, max fan-in = 7)Comparison DepthLUTsArray size (clusters) Area (μm 2 ) Delay (ns) DepthCMOS cells Array size (clusters) N Nano- devices Area (μm 2 ) Delay (ns) A CMOS /A CMOL A nanoPLA /A CMOL alu47127419×191377005.123185422×225978810044.01370.28 apex28160221×211660506.026192821×216113659144.61823.09 apex46114734×344146195.519117618×18677816723.66170.58 bigkey3181022×221933883.120206520×206102078292.72331.82 clma16677942×4262319413.175758567×67248746930810.2671.74 des6126319×191483314.228232123×2361261010974.51353.21 diffeq1498716×161002386.073200424×24610799119410.4842.27 dsip3136219×191483313.226161520×20799058293.41791.63 elliptic18214224×242136388.681479947×47425415458112.7471.63 ex10108405033×333913319.043298641×4132874634865.71120.28 ex5p795016×161002385.12790220×20468758294.31210.19 frisc23232025×2523085011.3114471545×45425869419917.6552.64 misex37117818×181245385.324139722×224921110043.61240.56 pdc9390132×323690569.654475249×4921484149796.8740.15 s29815168221×2116605010.745103020×204101618298.12001.33 s3841711477336×364627137.352828967×6735315693087.2501.24 s385849442235×354384134.864650269×6935027598728.844- seq7142720×201513695.423183225×2541102712964.01171.15 spla8333130×303260257.340424038×3832480829945.81090.12 tseng1378114×14784696.375186624×2464918119411.5662.48 CMOL FPGA: RESULTS (II) Toronto 20 benchmark circuit set D. Strukov and K.L. (2006a)

21. ITRS ERD July 200821 20092010201120122013Comments Half-pitch F CMOS (nm)5045403632Follows ITRS until 2013 Half-pitch F nano (nm)2018161412Mostly nanoimprint Device density n (Giga/cm 2 )637798128174Grows fast Parameter r10 11 Connectivity N100 121 Barely change Interface rotation angle  (  ) 5.7 5.2 Nanowire segment L (μm)4.03.63.22.83.0Decreases slowly Defect fraction q (%)20151075Improves fast DIGITAL CMOL: PROSPECTS (I) 20162019202220252028Comments Half-pitch F CMOS (nm)3028262422Decreases very slowly Half-pitch F nano (nm)10643.53EUV? Block-copolymers? Device density n (Tera/cm 2 )0.250.701.02.02.8Unprecedented density reached Parameter r1219262830Increases substantially Connectivity N144361676784900Increases fast Interface rotation angle  (  ) 4.83.02.22.01.9Decreases Nanowire segment L (μm)2.84.35.4 Increases slowly Defect fraction q (%)310.30.10.03Improves slower K. L. and D. Strukov (2007)

22. ITRS ERD July 200822 DIGITAL CMOL: PROSPECTS (II) Metrics (units)20092010201120122013Comments Half-pitch F CMOS (nm)5045403632In accordance with ITRS Half-pitch F nano (nm)2018161412- CMOS memories (Gbits/cm 2 )6.78.210.51316Follows ITRS (with A = 6F 2 CMOS ) CMOL memories (Gbits/cm 2 )410233667Initial progress impacted by q CMOS FPGA (Mgates/cm 2 )0.40.50.60.81.0Rescaled from 0.18 μm rules CMOL FPGA (Mgates/cm 2 )6257751,0001,2001,500- Metrics (units)20162019202220252028Comments Half-pitch F CMOS (nm)3028262422Grows slower than in ITRS Half-pitch F nano (nm)10643.53- CMOS memories (Gbits/cm 2 )1821252935Follows A = 6F 2 CMOS CMOL memories (Gbits/cm 2 )1003509001,2001,700Spectacular progress at lower q CMOS FPGA (Mgates/cm 2 )1.11.31.51.72.1Rescaled from 0.18 μm rules CMOL FPGA (Mgates/cm 2 )1,7002,0002,3002,7003,200- K. L. and D. Strukov (2007)

23. ITRS ERD July 200823 SAMPLE DSP TASK: CONVOLUTION (e.g., for FPA image processing) Parameters selected for our estimates: N = 1,024 F = 32 (i. e. << N) Accuracy: n S = n  = 12 Demands to hardware: Add-multiplies: F 2 N 2  10 9 per frame CMOS μ-processor: ~ 100 ms per frame D. Strukov and K. L. (2007b)

24. ITRS ERD July 200824 TWO NEW CELLS: Control cell:New (programmable) latch: inout clk IWIW ININ IEIE ISIS OEOE OWOW OSOS ONON CWCW ~C W ~C E CECE CSCS ~C S CNCN ~C N added CMOS line for control logic output pin input pin (not used) gnd Vdd 8 F CMOS Footprint: (3×8 F CMOS ) 2

25. ITRS ERD July 200825 S 12 bits out in T 32 bits in φ (12 bits) 32-bit Kogge Stone Adder 1010 cT 12-bit Wallace Tree Multiplier (Partial Product Generation and Reduction) out in M 24 bits 120120 cM 32 bits 24 bits 12 bits cAcB 0101 1010 0 multiplier adder multiplexer other Control cell Programmable latch cell used not used used not used Basic cell not used ARCHITECTURE AND PERFORMANCE Calculated performance for N = 1,024, F = 32, n = 12 bits: ~ 25 μs, vs. ~3,500 μs for CMOS (per frame) D. Strukov and K. L. (2007b)

26. ITRS ERD July 200826 NEUROMORPHIC NETWORKS (“CROSSNETS”) w jk = {-1, 0, +1} Generic structure of a feedforward CrossNet S. Fölling et al. (2001) O. Turel et al. (2004) Basic idea: CMOS “somas” + nanowire “axons” and “dendrites” + nanodevice “synapses” soma j soma k jk + jk - + + - - ji w ij

27. ITRS ERD July 200827 (@ 33 nanodevices per synapse, F nano = 3 nm, connectivity 10 4 ): Synapse footprint: ~ 500 nm 2 Synapse density: ~ 2  10 11 cm -2 (> 10 12 cm -2 bits/cm 2 ) Neural cell density: ~ 5  10 7 cm -2 (cf. 1.5  10 7 cm -2 in bio) Intercell latency: ~ 20 ns @ 100 W/cm 2 (R ~ 10 10  ) or: ~ 2,000 ns @ 1 W/cm 2 (R ~ 10 12  ) (cf. ~10 ms in bio) CMOL is the first hardware capable of challenging human’s cerebral cortex CROSSNETS: PERFORMANCE ESTIMATES Ö. Türel et al. (2004)

28. ITRS ERD July 200828 From: T. Hynton (DARPA), March 2008

29. ITRS ERD July 200829 ANOTHER CMOL SPECIES: HPL’s FPNI G. Snider and R. S. Williams (2007)

30. ITRS ERD July 200830 WEI WANG’s “3D CMOL” D. Tu et al. (2007) Features: - simpler interface pins - twice smaller area

31. ITRS ERD July 200831 SINGLE-ELECTRON LATCHING SWITCH: POSSIBLE MOLECULAR IMPLEMENTATION naphthalenediimide group as a single-electron transistor island perylenediimide group as a single-electron trap island Andreas Mayr (SBU) in: K. Likharev et al. (2003) (C 6 H 13 -) OPE bridges as tunnel junctions non-conducting support group isocyanide attachment group

32. ITRS ERD July 200832 theoretical result… …and experiment NDR IN MOLECULAR-SCALE SETs N. Simonian, J. Li, and K. L. (2007) S. Khondaker et al. (2004) NDR effect: unexpected, but in the hindsight, natural: V sd = 0:eV sd ~ U: i.e. current is determined by the highest barrier (giving the lowest tunneling rate) one barrier suppressed, another enhanced  current drops! NDR!

33. ITRS ERD July 200833 NDR CMOL CONCEPT Goto pair clock t 0 t 0 t 0 t 0 phase 1 phase 2 phase 3 phase 4 REF EVAL OFF Four-phase clocking Logic gates V I 0 V DD VtVt V CLK V GND upper layer nanowire lower layer nanowire V CLK2 V gnd V BIAS V OUT V CLK1 V gnd V CLK1 V gnd V IN2 V IN1 3 1 2 REFEVAL 3 1 2 Latching to Boolean “1” D. Strukov and K.L. (2007c)

34. ITRS ERD July 200834 NDR CMOL (preliminary results) Pros Different logic gates Small cell area (×3↑) Nanoscale latch (×1.5↑) Cons Low fan-in Dual rail logic (×2↓) Low fan-out (×1.15↓) Pipeline buffers (×1.25↓) Circuit CMOL FPGACMOL NDR Cells Area (μm 2 ) Cells Area (μm 2 ) alu439027499384389 apex2444783011516478 apex430275317525312 bigkey472567214334594 clma268596272862923579 des5422100412872534 diffeq554083012524519 dsip397560013174546 elliptic174432399299581242 ex101098621745320801330 ex5p30365317128296 frisc176462542287581193 misex332836009192381 pdc192603488505322096 s298255246714633607 s38417415766277808623354 s38584290094202592222456 seq490291511832491 spla167642996446221851 tseng591183010164422 Toronto 20 benchmark set Early summary (compared to CMOL FPGA) Area Comparable Delay Comparable Defect tolerance Comparable Data throughput Much better Better architecture possible? D. Strukov and K.L. (2007c)

35. ITRS ERD July 200835 CONCLUSIONS CMOS/Nano Hybrids: - possibly, the only way to go beyond the conventional lithography limits - realistic components, demos above ~15 nm Possible Impact: - extending Moore’s Law for 10 to 15 years beyond ITRS 32 nm point - eventually, first challenge to the cerebral cortex Hardware Issues: - F nano > 10 nm: integration / reproducibility - F nano < 10 nm: everything: - devices (SAM?) - patterning EUV IL? block-copolymer? - back-end-compatible pins Software Issues: - ASIC performance (vs CMOS) - tolerance to various defects - advanced information processing tasks and methods need better CAD tools

36. ITRS ERD July 200836 THANK YOU! comments/suggestions to: klikharev@notes.cc.sunysb.edu