1. CSET 4650 Field Programmable Logic Devices
Introduction to FPGAs
Field Programmable Gate Arrays
CSET Field Programmable Logic Devices
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2. Hierarchy of Logic Implementations
The diagram below is a modified version of the one we first used to discuss the role of FPLDs in logic implementation
This version more closely reflects the details as we have come to know them
Logic
Standard
ASIC
Programmable
Logic Devices
(FPLDs)
Gate
Arrays
Cell-Based
ICs
Full Custom
CPLDs
SPLDs
(e.g., PALs)
FPGAs
TTL
CMOS
SemiCustom

3. FPGA Development FPGAs evolved from Gate Arrays
Parallel with development of CPLDs
ASIC
Programmable
Logic Devices
(FPLDs)
Gate
Arrays
Cell-Based
ICs
Full Custom
CPLDs
SPLDs
(e.g., PALs)
FPGAs
SemiCustom

4. Gate Array Technology (1970s)
Mask-Programmable Logic Devices
MPLDs as compared to FPLDs
Programmed as part of fabrication process
Mask-Programmable Gate Arrays
A specific type of MPLD
Build standard layout of transistors on chip
Customer specifies wiring to connect transistors into gates and gates into systems
Only has to go through last few mask steps of fabrication process
Faster than full-custom chip fabrication
Mask-Programmable Gate Arrays are also called “sea of gates” layout
PLDs grew out of lookup approach where entire logic table could be programmed into PROM, inputs (address) selected data (logic outputs)
AND/OR plane represents wired-OR of data (draw on board)
Evolved into current CPLDs, which have configurable logic blocks at periphery of PLD planes. Combining flexibility of CLBs and speed of wired or

5. Gate Array Technology (1970s)
Simple logic gates
Use transistors to implement combinational and sequential logic
Interconnect
Wires to connect inputs and outputs to logic blocks
I/O blocks
Special blocks at periphery for external connections
Add wires for connections
Done when chip is fabricated
“mask-programmable logic device”
Construct any circuit

6. Evolution of the FPGA Early FPGAs
Used mainly for “glue logic” between other components (interfacing)
Simple Combinational Logic Blocks (CLBs)
Small number of inputs and outputs
Focus was on implementing “random” logic efficiently
As capacities grew, other applications emerged
FPGAs used as an alternative to custom IC’s for entire applications
Computing with FPGAs

7. Evolution of the FPGA
FPGAs have changed to meet new application demands
Carry chains, better support for multi-bit operations
Integrated memories, such as the block RAMs
Specialized units, such as multipliers, to implement functions that are slow/inefficient in CLBs
Newer devices incorporate entire CPUs:
Xilinx Virtex II Pro has 1-4 Power PC CPUs
Devices that don’t have CPU hardware generally support synthesized CPUs

8. Current FPGAs: Major Elements
Current commercial FPGAs have the same general structure but differ among major components:
Programmability
Technology used to program device
Internal logic cell structure
Combinational and sequential
Complexity
Routing mechanisms
Interconnecting wires and their layout

9. The Plan for Today
We will look at a generalized overview of FPGAs and their structure
More of our examples than not will be from Xilinx devices
Since that is what we use in the lab
Since they are recognized as a leading vendor
Over the next few meetings, we will look at greater detail about the major FPGA elements and families

10. General FPGA Architecture
Routing mechanism
Logic cell, often called a CLB – “configurable logic block”

11. Field-Programmable Gate Arrays
Based on Configurable Logic Blocks (CLB) as the logic cells …
CLB

12. Current FPGAs: Logic Cells
Current commercial FPGAs use logic cells that are based one one or more of the following:
Transistor pairs
Basic small gates
e.g., two-input NAND or XOR
Multiplexers
Look-up tables (LUTs)
Wide-fan-in AND-OR structures
Microprocessor-like

13. Field-Programmable Gate Arrays
Requires some form of programmable interconnect at crossovers …

14. Current FPGAs: Programming
Static RAM
Switch is a pass transistor controlled by the state of the SRAM bit
EEPROM
Switch is a floating-gate transistor that can be turned off by injecting charge onto its floating gate
Antifuse
Switch is a device that, when electrically programmed, forms a low resistance path

15. Current FPGAs versus MPLDs
Programmable switches
occupy larger chip areas
exhibit higher parasitic resistance and capacitance (power dissipation and propagation delay result)
Additional chip area required for switch programming circuitry
The more switches, the more flexible
Flexibility requires higher “overhead”
FPGAs are slower than MPLDs

16. Current FPGAs: Programming
Antifuse-
programmed
SRAM-
programmed
EPROM-
programmed
Island
Cellular
Actel ACT1 & 2
Quicklogic’s pASIC
Crosspoint’s CP20K
Altera’s MAX
AMD’s Mach
Xilinx’s EPLD
Xilinx LCA
AT&T Orca
Altera Flex
Toshiba
Plesser’s ERA
Atmel’s CLi

17. FPGA Architectures
FPGAs are commercially available in many different architectures and organizations.
Although each company’s offerings have unique characteristics, FPGA architectures can be generically classified into one of four categories:
Symmetrical Array
Row Based
Hierarchical PLD
Sea of Gates

18. FPGA Architectures
The Configurable Logic Blocks (CLBs) are organized in a two dimensional array separated by horizontal and vertical wiring channels.
Each CLB contains flip-flop(s), multiplexers, and a combinatorial function block which operates as an SRAM based table look-up.
Connections between CLBs are customized by turning on pass transistors which selectively connect the CLBs to the interconnection resources
CLB

19. FPGA Architectures
Pass transistors selectively connect the interconnect lines between the horizontal and vertical wiring channels.
SRAM cells which are distributed around the chip hold the state of the interconnect switches.
Surrounding the CLB array and interconnect channels are the programmable I/O blocks which connect to the package pins.
CLB

20. FPGA Architectures Xilinx XC4000 FPGA
Greater logic capacity per CLB is achieved using a two-level look-up table
Compared to earlier families, the routing resources have been more than doubled.
number of globally distributed signals has increased

21. FPGA Architectures
This organization is similar to that found in the traditional style of Mask Programmed Gate Arrays (MPGAs).
Vertical interconnect segments of varying lengths are available.
Vertical segments in input tracks are permanently connected to logic module inputs, and vertical segments in output tracks are permanently connected to logic module outputs.

22. FPGA Architectures
Long vertical segments are available which are uncommitted and can be assigned during routing.
The horizontal wiring channel resources are also segmented into varying lengths.
The minimum horizontal segment length is the width of a single logic module, and the maximum horizontal segment length spans the full channel.

23. FPGA Architectures
Any segment that spans more than one-third of the row length is considered a “long horizontal segment”.
Dedicated routing tracks are used for global clock distribution and for power and ground tie-off connections.

24. FPGA Architectures
The Actel ACT family FPGAs a logic module matrix is arranged as rows of cells separated by horizontal wiring channels
This organization is similar to that found in the traditional style of Mask Programmed Gate Arrays (MPGAs)

25. FPGA Architectures
This architecture represents a hierarchical arrangement of CLBs using a two-dimensional array structure.
Interconnections are via a centralized programmable interconnect structure
CLBs can be cascaded
I/O structures not shown

26. FPGA Architectures
The Altera Multiple Array MatriX (MAX) architecture represents a hierarchical arrangement of Erasable Programmable Logic Devices (EPLDs) using a two-dimensional array structure.
The design provides multiple level logic, uses a programmable routing structure, and is user reprogrammable based on EPROM or EEPROM technology.

27. FPGA Architectures
this design has a two-dimensional mesh array structure which resembles the gate array “sea of gates”
Static RAM programming technology is used to specify the function performed by each logic cell and to control the switching of connections between cells.

28. FPGA Architectures
The CAL1024 design contains 1024 identical logic cells arranged in a 32 X 32 matrix.
The design is considered to be a mesh-connected architecture since each cell is directly connected to its nearest north, south, east, and west neighbors.
In addition to these direct connects, two global interconnect signals are routed to each cell to distribute clock and other “low skew requirement” control signals.

29. Field-Programmable Gate Arrays
Xilinx Spartan-3 die image; note the regularity…

30. Field Programmable Gate Arrays
Xilinx FPGAs are based on Look-up Tables (LUTs) as the CLB.
A LUT is simply a representation of a truth table:
three-input truth table C 1 B A F a b c f
LUT
The function is programmable – any LUT can be programmed to be any function
three-input Look-Up Table
FPGAs are just a whole lot of LUTs with lots of interconnect

31. Synthesizing Functions to CLBs
Flexibility of CLBs is a big win -- much harder to map to technology with less-flexible blocks
Basically, can divide logic into n-input functions, map each onto a CLB.
Tools may have special-purpose routines for common blocks (like adders)
Harder problem: Placing blocks to minimize communication, particularly when using carry chains

32. FPGA Organization I/O1 a b c f a b c f a b c f I/O3 I/O2 a b c f a b c
x x x x x x x x
LUT a b c f
x x x x x x x x
LUT a b c f
x x x x x x x x
LUT
I/O3
I/O2 a b c f
x x x x x x x x
LUT a b c f
x x x x x x x x
LUT a b c f
x x x x x x x x
LUT
I/O4

33. FPGAs Xilinx FPGAs are based on SRAM Capacity
Lose programming when power is turned off
Can be programmed by a computer or by a special EPROM
Capacity
May have up to 10,000,000 gate equivalent
Up to 1,200 I/O pins

34. FPGAs
FPGAs must add some kind of switch to the equation to be user programmable.
The size and performance of the switch essentially determines the architecture
ULM (Universal Logic Module) must be as small as possible to maximize versatility and utilization

35. What’s in a CLB?
Most mapping seems to favor early utilization of LUTs in designs I have done.
Determining how much logic to include in a CLB is an on-going debate.

36. CLB Variables Number of inputs to LUT How is logic implemented
Trade off number of CLBs required vs. size of CLB and routing area
How is logic implemented
LUT vs. programmable and-or-invert vs. other
Technology used to hold configuration (program) of CLB
Flip-flop in CLB?
Additional Functionality
Carry chains
Consider your requirements. Carry function important for DSP apps, for example, , less utilized for other logic circuits.

37. Switch Detail Programmable Switch Matrix
Connections are controlled by RAM bits
More later

38. Programmable Switch Matrix
programmable switch element
turning the corner, etc.

39. The Fitter’s Job Partition logic functions into CLBs Arrange the CLBs
Interconnect the CLBs
Minimize the number of CLBs used
Minimize the size and delay of interconnect used
Work with constraints
“Locked” I/O pins
Critical-path delays
Setup and hold times of storage elements

40. Input-Output Blocks One IOB per FPGA pin Inputs
Allows pin to be used as input, output, or bidirectional (tri-state)
Inputs
Direct
Registered
Drive dedicated decoder logic for address recognition
IOB may also include logic for boundary scan (JTAG)

41. I/O blocks
Looks like a CPLD macrocell

42. Xilinx 4000-series FPGAs

43. FPGAs: Summary
Historically, FPGA architectures and companies began around the same time as CPLDs
FPGAs are closer to “programmable ASICs” - large emphasis on interconnection routing
Timing is difficult to predict - multiple hops vs. the fixed delay of a CPLD’s switch matrix.
But more “scalable” to large sizes.
FPGA configurable logic blocks have a few inputs and 1-2 flip-flops, but there are many more of them compared to the number of macrocells in a CPLD.

44. Common CPLD & FPGA Problems
Pin locking
Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout.
Locking too early may make the resulting circuit slower or not fit at all.
Running out of resources
Design may “blow up” if it doesn’t all fit on a single device.
On-chip interconnect resources are much richer than off-chip.
Larger devices are exponentially more expensive.

45. FPGAs: Pros Reasonably Cheap
Good for low-volume parts, more expensive than IC for high-volume parts
Short Design Cycle (~1sec programming time)
Reprogrammable
Can download bug fix into units you’ve already shipped
Large capacity (4 million gates or so, though we won’t use any that big)
FPGAs in the lab are “rated” at 300K gates
More flexible than PLDs -- can have internal state
More compact than MSI/SSI
Can be permanent (often used for mass production by gang programmers) or SRAM based. Manufacturing environment easily translates between the two. For example, if you do a design in our SRAM Xilinx Virtex, can be converted to fuse-type part, laser or masked programmed array, or even ASIC by software only. Justification: purely volume driven
“Cheap” means from $2-3 at low end up to $1000 for newest (densest) parts
Why start a new design with a $1K part? Prices fall very rapidly such that any outlay at beginning of design cycle (which might save converting a partitioned part to single unit later) is often justified by price drop when entering production. Example: start engineering on a $1K 4M gate part and you might be going to production 8 months later on a $200 part.
Major wins: cheap and quick to use
Key point: You share production costs with all other users of the part; it’s as if you got together with every other FPGA designer and agreed upon a common format (e.g. CLBs) and chipped in to have millions of wafers made.

46. FPGAs: Cons
Lower capacity, speed and higher power consumption than building an integrated circuit
Sub-optimal mapping of logic into CLB’s
Less dense layout and placement due to programmability
Overhead of configurable interconnect and logic blocks
PLDs may be faster than FPGA for designs they can handle
Need sophisticated tools to map design to FPGA
CPLDs always faster. Tip: using same vendor CPLD, say Xilinx, aids merging and simulating mixed design.
Cons nearly always deal with size and performance, which are two factors geometrically diminishing with feature size.
Because the pros, price and design cycle times, continue to drop, and the cons, size and speed, increase with technology, the trends favor FPGAs for future design work and FPGA designers for future employment.