1. Low Power via Sub-Threshold Circuits Mike Pridgen

2. “Logic Circuits Operating in Subthreshold Voltages” – Jabulani Nyathi and Brent Bero “Sub-Threshold Design: The Challenges of Minimizing Circuit Energy” – B.H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan 2

3. Goal of Sub-Threshold Circuits Minimize energy – Utilize leakage currents – Sacrifice speed 3

4. Uses of Sub-Threshold Circuits Standalone, low power devices – Wireless sensor nodes – RFID tags Burst-mode applications – Short, intensive bursts – Long, near-idle periods 4

5. Sub-Threshold FFT 16 bit FFT FFT lengths of 128 to 1024 350mV V DD 10kHz 155nJ / FFT – 350x better than microprocessor – 8x better than ASIC 5

6. Improving Performance by Changing V BULK nMos – V BULK = 600mV pMos – V BULK = 0V 0 – 380mV I D increases by 10x Never “OFF” – I D > 0.1nA 6

7. Body Biasing Types Traditional Three main variations – SBB – DTMOS – ABB Plus many others 7

8. Traditional Biasing nMos V BULK = GND pMOS V BULK = V DD Traditional CMOS Inverter 8

9. Switched Body Biasing nMos V BULK = V DD pMos V BULK = GND V DD < V TH SBB CMOS Inverter 9

10. Dynamic Threshold V BULK = V G Off if V DD > V TH DTMOS Inverter 10

11. Adjustable Bulk Bias V DD < V TH V DD > V TH Tunable – Low Power – High Speed – TBB TBB Inverter 11

12. Shorter Delays 12 6 – 10x speedup

13. Improving Performance Increased V DD = Increased Speed V DD =.75V TH versus V DD =.5V TH – 8x faster Bias scheme irrelevant – More power 13

14. Noise Effects TBB versus Traditional V DD = 376.2mV Logic 0 – 0 to 200mV Logic 1 – 225 to 376.2mV SBB noise margins worse 14

15. Standard (6T) SRAM Adjacent cells leakage current Fails Static Noise Margins 15

16. Conclusions Bias schemes increase performance Speed versus Power Slight increase in noise 6T SRAMS unusable 16

17. Questions