1. 1 APV25 I 2 C parameters Brief reminder of what the I2C registers do (from User Manual) Check on integration centre currently used parameters: TIB/TOB/TEC (thanks to Mariarosaria D’Alfonso, Andrea Rizzi, Katja Klein, Gaelle Boudoul) VPSP scan considerations Some information from APV wafer test database on production uniformity e.g. how well will chips match without individual tuning Pointers to reference information m.raymond@imperial.ac.uk - July '06

2. 2 APV25 analog chain IPRE IPCASC IPSF ISHA ISSF IPSP IMUXIN VFP VFS VPSP MUXGAIN IPRE, IPCASC, IPSF, ISSF, IPSP, IMUXIN, ISHA currents provided by bias generator to set operating points of analogue stages 8 bit values 0 -> 255 (read/write register access) VFP, VFS, VPSP voltages generated by dumping programmable currents into on-chip resistors 8 bit values 0 -> 255 (read/write register access) ISHA and VFS are “free” parameters for tuning pulse shape, but can specify default values VPSP is “free” parameter for analogue baseline adjust – but watch power consumption (see later)

3. 3 APV mode register (R/W) 8 bit register – only 6 bits used bit no. 5preamp polarity0 = non-inverting 1 = inverting 4 readout frequency0 = 20 MHz1= 40 MHz 3readout mode0 = decon. 1 = peak 2 calibration inhibit0 = OFF 1 = ON 1trigger mode0 = 3 sample1 = 1 sample 0 analogue bias0 = OFF1 = ON examples: binary dec. 100101 37 inverting, 20 MHz, decon., cal inhibit ON, 3 sample, bias ON 101111 47 inverting, 20 MHz, peak, cal inhibit ON, 1 sample, bias ON 100001 33 inverting, 20 MHz, decon., cal inhibit OFF, 3 sample, bias ON 101011 43 inverting, 20 MHz, peak, cal inhibit OFF, 1 sample, bias ON normal operation no CAL normal operation with CAL

4. 4 MUX gain (R/W) 8 bit register – only 5 bits used feature included to accommodate extreme process variations in on-chip resistor values bit no. 4 highest 3higher 2 nominal0 = OFF 1 = ON 1lower 0 lowest binary dec. 10000 16 +20% 01000 8 +10% 00100 4 nominal 00010 2-10% 00001 1 -20%

5. 5 Calibration and Latency (R/W) Calibration - 8 bit registers CDRVmask (all ones except one you want to drive) e.g. 11101111 CSELmask (all ones except delay you want to select – 8 steps of 3.125 nsec) there is a mistake in the user manual here! ICALcalibration pulse amplitude not well controlled – relies on small overlap region between two metal tracks so can use to “calibrate” (tune) pulse shape, but not gain Latency - 8 bit register sets separation between write and trigger pointers to the pipeline can take any value up to 191 if changed then must issue Reset101 to relaunch pipeline pointers otherwise chip will malfunction and latency error generated

6. 6 Error Register (Read only) 8 bit register – only 2 bits used bit 1FIFO error (overflow – should not happen (APVE protects)) bit 0 Latency error (distance between write and trigger pointers to pipeline not equal to programmed latency)  can (should) only return: bin. dec. 000no errors 011latency error 102FIFO error 113latency and FIFO error SEU effects may well cause these errors if chip detects either error then error bit also set in output data header

7. 7 TIB TOB TEC+ TEC- IPRE98989898 IPCASC52525252 IPSF34343434 ISHA46808080 ISSF34343434 IPSP55555555 IMUXIN34343434 ISPARE0000 ICAL40404040 VFP30303030 VFS70503050 VPSP37343733 CDRV0000 CSEL8888 MODE47374737 LATENCY100100100100 MUXGAIN4444 ERROR0111 Integration centre parameters currently in use all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only WARM (room temp. ~ +30) discrepancy may account for small differences observed in TEC+/TEC- performance?

8. 8 TIBTOBTEC IPRE858585 IPCASC454545 IPSF303030 ISHA305050 ISSF303030 IPSP484848 IMUXIN303030 ISPARE000 ICAL404040 VFP303030 VFS705060 VPSP37-- CDRV0-- CSEL8-- MODE47-- LATENCY100100100 MUXGAIN444 ERROR000 Parameters currently in use and proposed all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only COLD (-10 -> -20) values used by TIB provided by Andrea Rizzi in agreement with: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf values for TOB/TEC are what I propose here in agreement with: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf

9. 9 Parameters currently in use and proposed WARM (room temp.) TIB TOB TEC+ TEC- TIBTOBTEC IPRE98989898858585 IPCASC52525252454545 IPSF34343434303030 ISHA46808080305050 ISSF34343434303030 IPSP55555555484848 IMUXIN34343434303030 ISPARE0000000 ICAL40404040404040 VFP30303030303030 VFS705030(50)50705060 VPSP3734373337-- CDRV00000-- CSEL88888-- MODE4737473747-- LATENCY100100100100100100100 MUXGAIN4444444 ERROR0111000 all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only COLD (-10 -> -20) suggest default VFS (prior to tuning) -> 50 for TEC+ unless this causes problems for comparisons with previously measured data

10. 10 be careful with VPSP scans analogue baseline VPSP setting adjusts analogue baseline position works by introducing DC voltage offset at APSP O/P which in turn produces DC offset current flowing in the MUX stages baseline setting has strong effect on overall power e.g. assume baseline tuned to ~ 25% relative to dig. head amp. get ~7% power increase if move from 25% to 50% level much more (~ 28%) if scan through full range for setting up, better to start with high value (low baseline) and scan down (baseline rises) until target value reached (then stop) see: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/Detailed%20APV25%20Power%20Consumption.pdf 0 100% 50% module power baseline pos’n TIB module measurement

11. 11 Some info from APV production test data ~ 600 wafers (~ 216,000 chips) tested over ~ 4 years including early production wafers with yield problems which were not used production lots from lot 9 onwards individual chips subjected to detailed testing of analogue/digital functionality -> Known Good Die (KGD) individual chip results stored => analysis of database -> insight into overall uniformity note: I2C parameters used in production test kept constant throughout (including ISHA and VFS) except for VPSP Production wafer yields (360 chips / wafer)

12. 12 intensity plots show pulse shapes from all 131,734 KGD from 414 production wafers (lots 9 – 29) overlaid SPICE simulated peak mode pulse shapes show almost all chips lie within  1  of nominal Normalised Pulse Shapes peak mode deconvolution => pulse shapes match quite well even without tuning

13. 13 VFS fixed, vary ISHA ISHA fixed, vary VFS Pulse shape tuning strong effect on decon pulse shape weak effect strong effect on peak pulse fall time

14. 14 Output Frame Parameters APV output frame consists of digital header followed by 128 analogue samples digital header amplitude set by on-chip current reference mean header amplitude and spread for all KGD/lot shows minimal lot dependence average analogue pedestal (baseline) set by VPSP – the only parameter varied during wafer test (tuned to position baseline at 25% of digital header range) mean value and spread of distributions of VPSP values required to set 25% level show some lot dependence, but well within available adjustment range error bars show  1 std. dev. peak mode deconvolution

15. 15 lots of info and links at: http://www.hep.ph.ic.ac.uk/~dmray/Tracker.html I2C parameter recommendations for different temperatures: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf APV production data analysis LECC paper: http://indico.cern.ch/getFile.py/access?contribId=108&resId=0&materialId=paper&confId=0510 Reference information

16. 16 Transistor level – for info (1) IPRE IPCASCIPSFISHAISSF VFPVFS PREAMP SF INV preamp polarity select SHAPER pipeline

17. 17 Transistor level (2) IPSP IMUXIN VPSP MUXGAIN APSP