1. Explain giving examples as appropriate, the essential features of an instruction set of a CPU. Each instruction must contain 4 basic components: Operation code: specifies the operation to be performed, expressed as a binary code. Source operand references: operands required for the instruction are specified Result reference: where should the result of the operation be placed? Next instruction reference: how / where is the next instruction to be found An instruction set should be functionally complete and should permit the user to formulate any high-level data processing task. Explain giving examples as appropriate, the essential features of an instruction set of a CPU. Each instruction must contain 4 basic components: Operation code: specifies the operation to be performed, expressed as a binary code. Source operand references: operands required for the instruction are specified Result reference: where should the result of the operation be placed? Next instruction reference: how / where is the next instruction to be found An instruction set should be functionally complete and should permit the user to formulate any high-level data processing task.

2. 3 address instructions - Both operands and the result are explicitly contained in the instruction word – Example: X = Y + Z. 2 address instructions – One of the addresses is used to specify both an operand and the result location – Example: X = X + Y 1 address instructions – Traditional accumulator-based operations – Example: Acc = Acc + X 0 address instructions – This relies on use of registers only and no access to address bus is made directly. All addresses are implied, as in register-based operations Example: TBA (transfer register B to A) What types of instructions would a CPU typically be required to support

3. Explain briefly the steps that you would take to design an instruction set for a 16-bit CPU. 1.Decide on the instructions that you want to support as given above. Describe these in RTL notation for reference. 2.Allocate the number of bits that you need to accommodate all the instructions you identified in 1 above. i.e. for 16 instructions use 4 bits. 3.Decide the addressing mode for the operand fetch and allocate the bits for this (i.e. direct/indirect use 1 bit. This stage could be incorporated in 2 above to satisfy the number of instructions supported. Technically this now gives 32 possible instructions and that may be too many. 4.Allocate the rest of bit to the operand value

4. Decode the following code using the instruction set information provided below 0F FF 60 05 23 33 71 02

5. Convert hexadecimal to binary 0F = FF = 60 = 05 = 23 = 33 = 71 = 02 =

6. Convert hexadecimal to binary 0F = 0000 1111 FF = 1111 1111 60 = 0110 0000 05 = 0000 0101 23 = 0010 0011 33 = 0011 0011 71 = 0111 0001 02 = 0000 0010

7. Map 16 bits onto architecture diagram 0F = 0000 1111 FF = 1111 1111 => 60 = 0110 0000 05 = 0000 0101 => 23 = 0010 0011 33 = 0011 0011 => 71 = 0111 0001 02 = 0000 0010 =>

8. 00001111 1111 1111 01100000 0000 0101 00100011 0011 0011 01110001 0000 0110 Map 16 bits onto architecture diagram 0F = 0000 1111 FF = 1111 1111 => 60 = 0110 0000 05 = 0000 0101 => 23 = 0010 0011 33 = 0011 0011 => 71 = 0111 0001 02 = 0000 0010 =>

9. Convert opcode to instruction mnemonics 00001111 1111 1111 01100000 0000 0101 00100011 0011 0011 01110001 0000 0110

10. Convert opcode to instruction mnemonics and xplain what registers and memory are affected at each step LDA 0FFAC<-0FF SUB 5ACAC<AC-5 STA [333]M [333]<-AC;MEMORY LOCATION 333 STORES ACCUMULATOR VALUE WHICH IS CHANGING ACCORDING TO THE VALUE AC-5. JNZ [102]JUMP IF NOT ZERO to 102 i.e. loop while not zero 00001111 1111 1111 01100000 0000 0101 00100011 0011 0011 01110001 0000 0110