1. SoC Interconnect Modeling Venkata Krishna N. Dhulipala 11/20/2008

2. Relevance and Motivation Most embedded systems today are built using SoC (System on Chip) technology As technology advances delay of transistors and local interconnects scales down augmenting clock rates Since chip area is projected to increase, length of global interconnects increases and therefore their delay

3. Interconnect Modeling Resistance: R = (ρ/t ). (l/w), ρ=resistivity is constant for given metal l w s t h

4. Interconnect Modeling Capacitance: C = (ε ox /h). wl Coupling capacitance with adjacent wires ignored here – Gives rise to crosstalk Putting resistance and capacitance together  Delay, Τpd = RC A more detailed capacitance model is discussed in the report

5. Interconnect Modeling Inductance: Significant at higher frequencies, since impedance Z=R+jwL Introduces second order effects like, (a) Over/under-shoot edges, (b) L di/dt voltage drop, (c) Long range crosstalk, and (d) f-dependent R

6. Improve Timing Add signal Repeaters Effectively partition On and Off-chip interconnects Space and ground shielding to eliminate crosstalk Report shows mathematical derivations to minimize delay by addition of repeaters and partitioning

7. Current and Future Work Current Tools – Mantle by Magma (place and route), Primtime/Primetime-SI by Synopsys (timing and signal integrity analysis), Allegro by Cadence (chip-to-board interconnect modeling) Future & Research Parallel Repeater-Insertion – To account for inductance effects Interconnect delay aware RTL bus architectures Noise-rejection interconnect design