1. 1 Homework Reading –None (Finish all previous reading assignments) Machine Projects –Continue with MP5 Labs –Finish lab reports by deadline posted in lab

2. 2 Hierarchy for 80286 Memory and I/O IBM PC-AT (“Advanced Technology” in 1984) DOS 3.0 Operating System PC-AT bus evolved into Industry Standard Bus Many manufacturers built ISA-based PCs/cards ISA Bus –Slow 6 MHz evolved to 8 MHz or 125 nsecs/cycle –Address Bus 20 bits –Data Bus 16 bits

3. 3 IBM PC-AT Reference: http://www.vintage-computer.com/ibmpcat.shtml

4. 4 Big Picture (80286) RTCKeyboard Serial Port Parallel Port Floppy Disk 80286 RAM Memory ROM Memory ISA Bus: 20/16 bits, 8 MHz (125 nsecs/cycle) Hard Disk

5. 5 Hierarchy for 80486 Memory and I/O CPU Clock: 66 MHz Local Bus or CPU Bus –“Fast” 33MHz / 32 bits wide Expansion Bus Controller (CPU-ISA Bridge) ISA Bus (Legacy) –“Slow” 8 MHz or 125 nsecs/cycle –Address Bus 20 bits –Data Bus 16 bits

6. 6 Big Picture (80486)

7. 7 Competition for ISA replacement Many vendors proposed busses to replace ISA as the technology improved –IBM: Micro Channel Architecture (MCA) –Extended Industry Standard Architecture (EISA) –VESA Local Bus –Intel: Peripheral Component Interconnect (PCI) PCI had won commercial battle by mid-90’s –“Medium Speed”: 33 or 66 MHz / 32 or 64 bits wide For a while PCs had a mix of ISA and PCI slots

8. 8 Subsequent Evolution More and more of the “random logic” and VLSI chips surrounding the processor were included in Ultra-VLSI chips (“Motherboard chips”) The “North Bridge” allows highest speed access to program/data memory and high speed graphics processors (faster access than the PCI bus!) The “South Bridge” interfaces to PCI bus and incorporates devices for Ethernet, USB, etc. The Super I/O chip incorporates legacy interfaces –Floppy Disk, Keyboard, Parallel Port, Serial Ports, etc.

9. Hierarchy for Pentium Memory and I/O 9 Mother Board chip or chip set

10. Hierarchy for Pentium Memory and I/O

11. 11 Motherboard Chipsets The motherboard chip set provides the core logic and manages the motherboard's functions –CPU: CPU –NB: Northbridge –GPU: Graphics –SB: Southbridge Source: Wikipedia

12. Multi-core CPU Chips To increase processing power, multiple CPU’s are included in high performance CPU chips Example Dual core:

13. 13 Enhancing Performance “Pipelining is an implementation technique in which multiple instructions are overlapped in execution”, (Patterson and Hennessey, “Computer Organization and Design”, p. 436) Sequential Execution: Pipelined Execution:

14. 14 Enhancing Performance Pipelining improves the overall performance by increasing instruction throughput per unit time not decreasing execution time of an individual instruction Ideal speedup is number of stages in the pipeline Do we achieve this? Sometimes / Not always –Notice the idle time in the pipe at certain times –Flushing pipeline during conditional jumps –Data being calculated by previous instruction may be needed too early during the next instruction cycle

15. 15 Superscalar Processors IFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOSIFOFEXOS 0 1 2 3 4 5 6 7 8 9 Time in Base Cycles More than one execution pipeline executing in parallel Note: Possible coordination problems must be resolved

16. 16 Custom Digital Signal Processor Early example of a super scalar processor with pipelining of arithmetic operations Embedded application is hard real time system – processing analog modem waveforms Computations are based on complex arithmetic Rotation of a vector (e.g. carrier frequency) –Complex multiply Filtering of a sequence of signal samples –Loop doing complex multiplication and addition

17. 17 Digital Signal Processor Architecture Signal Processing Controller (SPC) Fetch and Execute Instructions Multiplier-Accumulator-Ram (Real) Multiplier-Accumulator-Ram (Imaginary) Data Bus Real MAR Chip SelectImaginary MAR Chip Select Address/Modulo Registers ALU Memory SPC Program Memory R0 R1 N0 N1 Controlling Host Processor (68000) Analog/Digital Converter From Phone Line Digital/Analog Converter To Phone Line Address Bus

18. 18 Addresses and Complex Data Addresses stored in SPC Registers –Pointers to complex data in MAR memories –Register post increment modes: Increment by one Decrement by one Increment by one modulo specified N register Decrement by one modulo specified N register Complex numbers stored in MAR memories: –Real part in one MAR (Real MAR) –Imaginary part in other MAR (Imaginary MAR)

19. 19 Multiplier-Accumulator-RAM X-RegisterY-Register Multiplier Adder 256 Words of RAM Memory Accumulator MPY MAC To Other MARFrom Other MAR Address from SPC Selector Chip Select From SPC Selector

20. 20 SPC/MAR Assembly Programming Complex Multiply (R R0 * R R1 – I R0 * I R1 ) + i (R R0 * I R1 + R R1 * I R0 ) YPP.PMP.R1Load both Y from own memory at R1 address MPY.PMR.R0Multiply both with real memory at R0 address YMM.RMI.R1Load minus real Y from imag memory at R1 address YPP.IMR.R1Load imag Y from real memory at R1 address MAC.PMI.R0Multiply/add both with imag memory at R0 address NOPResult not ready yet: NOP or housekeeping STA.PMP.R0Store each acc. in own memory at R0 address

21. 21 Moore’s Law Gordon Moore made a famous observation in 1965, just four years after the first planar integrated circuit was discovered Moore observed an exponential growth in the number of transistors per chip and predicted that this trend would continue Moore's Law, the doubling of transistors every couple of years, has been maintained, and still holds true today

22. 22 Moore’s Law

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