1. Computer Arithmetic

2. Arithmetic & Logic Unit
Does the calculations
Everything else in the computer is there to service this unit
Handles integers
May handle floating point (real) numbers
May be separate FPU (maths co-processor)
May be on chip separate FPU (486DX +)

3. ALU Inputs and Outputs

4. Integer Representation
Only have 0 & 1 to represent everything
Positive numbers stored in binary
e.g. 41=
No minus sign
No period
Sign-Magnitude
Two’s compliment

5. Sign-Magnitude Representation
simplest form of representation
If the sign bit is 0, the number is positive.
if the sign bit is 1, the number is negative.
In an n-bit word, the rightmost bits hold the magnitude of the integer.

6. Draw backs of Singed magnitude representation
Problems
Need to consider both sign and magnitude in arithmetic
Two representations of zero (+0 and -0)
sign-magnitude representation is rarely used in
implementing the integer portion of the ALU.
the most common scheme is twos complement representation

7. Two’s complement Representation
Uses the most significant bit as a sign bit, making it easy to test whether an integer is positive or negative
Range of numbers to be represented
-2n-1 to 2n-1-1
Unlike signed magnitude, there is only a single representation for number 0

8. Complements(quick revision)
There are two types of complements for each base-r system: the radix complement and diminished radix complement.
Diminished Radix Complement - (r-1)’s Complement
Given a number N in base r having n digits, the (r–1)’s complement of N is defined as:
(rn –1) – N
Example for 7-digit binary numbers:
1’s complement is (rn – 1) – N = (27–1)–N = –N
1’s complement of is – =
Observation:
Subtraction from (rn – 1) will never require a borrow
Diminished radix complement can be computed digit-by-digit
For binary: 1 – 0 = 1 and 1 – 1 = 0

9. Complements(revision)
Radix Complement
Example: Base-2
The r's complement of an n-digit number N in base r is defined as
rn – N for N ≠ 0 and as 0 for N = 0. Comparing with the (r  1) 's complement, we note that the r's complement is obtained by adding 1 to the (r  1) 's complement, since rn – N = [(rn  1) – N] + 1.
The 2's complement of is
The 2's complement of is

10. Two’s complement Representation(cont’d)
2’s Complement (Radix Complement)
Take 1’s complement then add 1
Toggle all bits to the left of the first ‘1’ from the right
Example:
Number:
1’s Comp.: OR 1 1

11. Two’s Compliment
+3 =
+2 =
+1 =
+0 =
-1 =
-2 =
-3 =

12. One representation of zero Arithmetic works easily
Benefits
One representation of zero
Arithmetic works easily
Negating is fairly easy
3 =
Boolean complement gives
Add 1 to LSB

13. The Arithmetic with Complements
Subtraction with Complements
The subtraction of two n-digit unsigned numbers M – N in base r can be done as follows:

14. Complements
Example 1.7
Given the two binary numbers X = and Y = , perform the subtraction (a) X – Y ; and (b) Y  X, by using 2's complement.
There is no end carry. Therefore, the answer is Y – X =  (2's complement of ) = 

15. Negation Special Case 1
0 =
Bitwise not
Add 1 to LSB
Result
Overflow is ignored, so:
- 0 = 0 

16. Negation Special Case 2
-128 =
bitwise not
Add 1 to LSB
Result
So:
-(-128) = X
Monitor MSB (sign bit)
It should change during negation

17. Range of Numbers 8 bit 2s compliment 16 bit 2s compliment
+127 = = 27 -1
-128 = = -27
16 bit 2s compliment
= =
= = -215

18. Conversion Between Lengths
Positive number pack with leading zeros
+18 =
+18 =
Negative numbers pack with leading ones
-18 =
-18 =
i.e. pack with MSB (sign bit)

19. Addition and Subtraction
Normal binary addition
Monitor sign bit for overflow
Take twos compliment of substahend and add to minuend
i.e. a - b = a + (-b)
So we only need addition and complement circuits

20. Hardware for Addition and Subtraction

21. Multiplication
Complex
Work out partial product for each digit
Take care with place value (column)
Add partial products

22. Multiplication Example
Multiplicand (11 dec)
x Multiplier (13 dec)
Partial products
Note: if multiplier bit is 1 copy
multiplicand (place value)
otherwise zero
Product (143 dec)
Note: need double length result

23. Unsigned Binary Multiplication

24. Execution of Example

25. Flowchart for Unsigned Binary Multiplication

26. Multiplying Negative Numbers
This does not work!
Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer
Solution 2
Booth’s algorithm

27. The algorithm shall be explained with the help of example
Booth’s Algorithm
Booth algorithm gives a procedure for multiplying binary integers in signed –2’s complement representation.
The algorithm shall be explained with the help of example
Example, (2)ten x (- 4)ten
0010 two * 1100 two

28. Step 1-Making The Booth Table
I. From the two numbers, pick the number with the smallest difference between a series of consecutive numbers, and make it a multiplier.
From 0 to 0 no change, 0 to 1 one change, 1 to 0 another change ,so there are two changes
From 1 to 1 no change, 1 to 0 one change, 0 to 0 no change, so there is only one change on this one.
Therefore, multiplication of 2 x (– 4), where 2ten (0010two) is the multiplicand and (– 4) ten (1100two) is the multiplier.

29. Step 1-cont’d
II. Let X = 1100 (multiplier) and Y = 0010 (multiplicand) Take the 2’s complement of Y and call it –Y,= 1110 III. Load the Multiplier Register(M) value in the table. IV. Load 0 for x-1 value it should be the previous first least significant bit of x V. Load 0 in Upper and Lower Product Register which will have the product of X and Y at the end of operation. VI. Make four rows for each cycle; this is because we are multiplying four bits numbers

30. Step 2-Booth Algorithm
Booth algorithm requires examination of the multiplier bits, and shifting of the partial product.
Prior to the shifting, the multiplicand may be added to partial product, subtracted from the partial product, or left unchanged according to the following rules:
Look at the first least significant bits of the multiplier “X”, and the previous least significant bits of the multiplier “X - 1”.

31. 1 0 Subtract Y from U, and shift or add (-Y) to U and shift
Step 2(cont’d)
0 0 Shift only
1 1 Shift only.
0 1 Add Y to U, and shift
1 0 Subtract Y from U, and shift or add (-Y) to U and shift
Take U & V together and shift arithmetic right shift which preserves the sign bit of 2’s complement number.
Thus a positive number remains positive, and a negative number remains negative.
III. Shift X circular right shift because this will prevent us from using two registers for the X value.

32. Booth(cont’d) Y=0010 and Y’=1110 Product Register Multiplier X-1
cycles U V 1 2 + 3 3a 4

33. Booth’s Algorithm

34. Example of Booth’s Algorithm

35. Division
More complex than multiplication
Negative numbers are really bad!
Based on long division

36. Division of Unsigned Binary Integers
Quotient
Divisor
1011
Dividend
1011
001110
Partial
Remainders
1011
001111
1011
Remainder
100

37. Flowchart for Unsigned Binary Division

38. Numbers with fractions Could be done in pure binary
Real Numbers
Numbers with fractions
Could be done in pure binary
= =9.625
Where is the binary point?
Fixed?
Very limited
Moving?
How do you show where it is?

39. Floating Point (a brief look)
4/22/2017
Floating Point (a brief look)
We need a way to represent
numbers with fractions, e.g.,
very small numbers, e.g.,
very large numbers, e.g., ´ 109
Representation:
sign, exponent, significand: (–1)sign * significand * 2exponent
more bits for significand gives more accuracy
more bits for exponent increases range
IEEE 754 floating point standard:
single precision : 8 bit exponent, 23 bit significand
double precision: 11 bit exponent, 52 bit significand

40. IEEE 754 floating-point standard
4/22/2017
IEEE 754 floating-point standard
Leading “1” bit of significand is implicit
Exponent is “biased” to make sorting easier
all 0s is smallest exponent all 1s is largest
bias of 127 for single precision and 1023 for double precision
summary: (–1)sign ´ (1+significand) ´ 2exponent – bias
Example:
decimal: = -3/4 = -3/22
binary : = -1.1 x 2-1
floating point: exponent = -1+bias = 126 =
IEEE single precision:

41. Floating Point Complexities
4/22/2017
Floating Point Complexities
Operations more complicated: align, renormalize, ...
In addition to overflow we can have “underflow”
Accuracy can be a big problem
IEEE 754 keeps two extra bits, guard and round, and additional sticky bit (indicating if one of the remaining bits unequal zero)
four rounding modes
positive divided by zero yields “infinity”
zero divide by zero yields “not a number”
other complexities
Implementing the standard can be tricky
Not using the standard can be even worse
see text for description of 80x86 and Pentium bug!

42. Floating Point Examples

43. Signs for Floating Point
Mantissa is stored in 2s compliment
Exponent is in excess or biased notation
e.g. Excess (bias) 128 means
8 bit exponent field
Pure value range 0-255
Subtract 128 to get correct value
Range -128 to +127

44. FP numbers are usually normalized
Normalization
FP numbers are usually normalized
i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1
Since it is always 1 there is no need to store it
Representation for non-integral numbers
Including very small and very large numbers
Like scientific notation
–2.34 × (normalized)
× 10–4 (not normalized)
× (not normalized)
In binary
±1.xxxxxxx2 × 2yyyy

45. FP Ranges For a 32 bit number Accuracy 8 bit exponent
The effect of changing lsb of mantissa
23 bit mantissa 2-23  1.2 x 10-7
About 6 decimal places

46. Expressible Numbers

47. Density of Floating Point Numbers

48. IEEE 754
Standard for floating point storage
32 and 64 bit standards
8 and 11 bit exponent respectively
Extended formats (both mantissa and exponent) for intermediate results

49. IEEE 754 Formats

50. FP Arithmetic +/-
Check for zeros
Align significands (adjusting exponents)
Add or subtract significands
Normalize result

51. FP Addition & Subtraction Flowchart

52. FP Arithmetic x/
Check for zero
Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
Round
All intermediate results should be in double length storage

53. Floating Point Multiplication

54. Floating Point Division

55. Required Reading
Stallings Chapter 9
IEEE 754 on IEEE Web site