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Computer ArchitectureFall 2008 © August 27, 2008 www.qatar.cmu.edu/~msakr/15447-f08/ CS 447 – Computer Architecture Lecture 4 Computer Arithmetic (2)

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Presentation on theme: "Computer ArchitectureFall 2008 © August 27, 2008 www.qatar.cmu.edu/~msakr/15447-f08/ CS 447 – Computer Architecture Lecture 4 Computer Arithmetic (2)"— Presentation transcript:

1 Computer ArchitectureFall 2008 © August 27, 2008 www.qatar.cmu.edu/~msakr/15447-f08/ CS 447 – Computer Architecture Lecture 4 Computer Arithmetic (2)

2 Computer ArchitectureFall 2008 © Last Time °Representation of finite-width unsigned and signed integers °Addition and subtraction of integers °Multiplication of unsigned integers

3 Computer ArchitectureFall 2008 © Unsigned Binary Multiplication

4 Computer ArchitectureFall 2008 © Execution of Example

5 Computer ArchitectureFall 2008 © Flowchart for Unsigned Binary Multiplication

6 Computer ArchitectureFall 2008 © Multiplying Negative Numbers °This does not work! °Solution 1 Convert to positive if required Multiply as above If signs were different, negate answer °Solution 2 Booth’s algorithm

7 Computer ArchitectureFall 2008 © Observation °Which of these two multiplications is more difficult? 98,765 x 10,001 98,765 x 9,999 °Note: 98,765 x 10,001 = 98,765 x (10,000 + 1) 98,765 x 9,999 = 98,765 x (10,000 – 1)

8 Computer ArchitectureFall 2008 © In Binary Let Q = d d d 0 1 1... 1 1 0 d d QL = d d d 1 0 0... 0 0 0 d d QR = 0 0 0 0 0 0... 0 1 0 0 0

9 Computer ArchitectureFall 2008 © In Binary Let Q = d d d 0 1 1... 1 1 0 d d QL = d d d 1 0 0... 0 0 0 d d QR = 0 0 0 0 0 0... 0 1 0 0 0 Then Q = QL – QR And M x Q = M x QL – M x QR

10 Computer ArchitectureFall 2008 © A bit more explanation P = M x Q where M and Q are n-bit two’s complement integers e.g., Q = -2 3 q 3 + 2 2 q 2 + 2 1 q 1 + 2 0 q 0 which can be re-written as follows: Q = 2 0 (q -1 –q 0 )+2 1 (q 0 -q 1 )+2 2 (q 1 -q 2 )+2 3 (q 2 -q 3 ) leading to P =M x 2 0 x (q -1 - q 0 ) + M x 2 1 x (q 0 - q 1 ) + M x 2 2 x (q 1 - q 2 ) + M x 2 3 x (q 2 - q 3 )

11 Computer ArchitectureFall 2008 © Finally! P =M x 2 0 x (q -1 - q 0 ) + M x 2 1 x (q 0 - q 1 ) + M x 2 2 x (q 1 - q 2 ) + M x 2 3 x (q 2 - q 3 ) qiqi q i-1 q i-1 – q i Action 000Noop 011Add M 10Subtract M 110Noop

12 Computer ArchitectureFall 2008 © Example of Booth’s Algorithm

13 Computer ArchitectureFall 2008 © Booth’s Algorithm

14 Computer ArchitectureFall 2008 © Division °More complex than multiplication °Negative numbers are really bad! °Based on long division

15 Computer ArchitectureFall 2008 © Division of Unsigned Binary Integers 001111 1011 00001101 10010011 1011 001110 1011 100 Quotient Dividend Remainder Partial Remainders Divisor

16 Computer ArchitectureFall 2008 © Flowchart for Unsigned Binary Division

17 Computer ArchitectureFall 2008 © Real Numbers °Numbers with fractions °Could be done in pure binary 1001.1010 = 2 4 + 2 0 +2 -1 + 2 -3 =9.625 °Where is the binary point? °Fixed? Very limited °Moving? How do you show where it is?

18 Computer ArchitectureFall 2008 © Floating Point °+/-.significand x 2 exponent °Misnomer °Point is actually fixed between sign bit and body of mantissa °Exponent indicates place value (point position) Sign bit Biased Exponent Significand or Mantissa

19 Computer ArchitectureFall 2008 © Floating Point Examples

20 Computer ArchitectureFall 2008 © Signs for Floating Point °Sign Magnitude for Mantissa °Exponent is in excess or biased notation e.g. Excess (bias) 127 8 bit exponent field Pure value range 0-255 Subtract 127 to get correct value Range -127 to +128

21 Computer ArchitectureFall 2008 © Normalization °FP numbers are usually normalized °i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1 °Since it is always 1 there is no need to store it °(c.f. Scientific notation where numbers are normalized to give a single digit before the decimal point °e.g. 3.123 x 10 3 )

22 Computer ArchitectureFall 2008 © FP Ranges °For a 32 bit number 8 bit exponent +/- 2 128  3.4 x 10 38 °Accuracy The effect of changing lsb of mantissa 23 bit mantissa 2 -23  1.2 x 10 -7 About 6 decimal places

23 Computer ArchitectureFall 2008 © Examples of 32-bit Numbers (wikipedia) TypeSignExpExp+BiasExponentSignificandValue Zero0-12700000 000 0000 0000 0000 0000 00000 One001270111 1111000 0000 0000 0000 0000 00001 Minus One101270111 1111000 0000 0000 0000 0000 0000 Smallest denormalized number*-12700000 000 0000 0000 0000 0000 0001 ±2 −23 × 2 −126 = ±2 −149 ≈ ±1.4×10 -45 Middle denormalized number*-12700000 100 0000 0000 0000 0000 0000±2 -1 × 2 -126 = ±2 -127 ≈ ±5.88×10 -39 Largest denormalized number*-12700000 111 1111 1111 1111 1111 1111±(1-2 -23 ) × 2 -126 ≈ ±1.18×10 -38 Smallest normalized number*-12610000 0001000 0000 0000 0000 0000 0000±2 -126 ≈ ±1.18×10 -38 Largest normalized number*1272541111 1110111 1111 1111 1111 1111 1111±(2-2 -23 ) × 2 127 ≈ ±3.4×10 38 Positive infinity01282551111 000 0000 0000 0000 0000 0000+∞ Negative infinity11282551111 000 0000 0000 0000 0000 0000-∞ Not a number*1282551111 non zeroNaN * Sign bit can be either 0 or 1

24 Computer ArchitectureFall 2008 © Range and Precision (wikipedia) ExponentMinimumMaximumPrecision 0121.19E-07 1242.38E-07 2484.77E-07 10102420481.22E-04 11204840962.44E-04 238388608167772151 2416777216335544302 1271.70E+383.40E+382.03E+31

25 Computer ArchitectureFall 2008 © Expressible Numbers

26 Computer ArchitectureFall 2008 © Density of Floating Point Numbers

27 Computer ArchitectureFall 2008 © IEEE 754 Formats

28 Computer ArchitectureFall 2008 © FP Arithmetic +/- °Check for zeros °Align significands (adjusting exponents) °Add or subtract significands °Normalize result

29 Computer ArchitectureFall 2008 © FP Addition & Subtraction Flowchart

30 Computer ArchitectureFall 2008 © Floating point adder

31 Computer ArchitectureFall 2008 ©

32 Computer ArchitectureFall 2008 ©

33 Computer ArchitectureFall 2008 © FP Arithmetic x/  °Check for zero °Add/subtract exponents °Multiply/divide significands (watch sign) °Normalize °Round °All intermediate results should be in double length storage

34 Computer ArchitectureFall 2008 © Floating Point Multiplication

35 Computer ArchitectureFall 2008 © Floating Point Division


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