1. International Technology Roadmap for Semiconductors Metrology Roadmap 2001 Update EuropeAlain Deleporte (ST)4/01 Alec Reader (Philips Analytical) Vincent Vachellerie (ST)4/01 Mauro Vascone (ST) JapanFumio Mizuno (MEISEI University) Mashiko Ikeno (NEW) Korea Taiwan Henry Ma (EPISIL) USSteve Knight (NIST) Bob Scace (Klaros Corporation) Jack Martinez (NIST) Alain Diebold (Int. SEMATECH)

2. International Technology Roadmap for Semiconductors AGENDA Overview 2001 2001 Difficult Challenges Lithography Metrology FEP Metrology Interconnect Metrology Materials & Contamination Characterization Grand Metrology Challenges

3. International Technology Roadmap for Semiconductors New to – Five Difficult Challenges 65nm / Before 2007 New to – Five Difficult Challenges 65nm / Before 2007 Key requirement for Cu/Damascene metrology is void detection in Cu lines and pore size distribution (find killer voids and pores) Scribe line shrinkage reduce test structure area making high precision measurements difficult in scribe lines.

4. International Technology Roadmap for Semiconductors SCOPE Microscopy Control of Statistical Processes Lithography Metrology FEP Metrology Interconnect Metrology Materials and Contamination Metrology Integrated Metrology Standards and Reference Materials

5. International Technology Roadmap for Semiconductors Determination of manufacturing Metrology when device and interconnect technology remain undefined. New to – Five Difficult Challenges 65nm / After 2007 New to – Five Difficult Challenges 65nm / After 2007

6. International Technology Roadmap for Semiconductors GAPS in FAB Ready Metrology 3D CD for Mask and Wafer for lines and contact/via and long term capability for CD Optical and Electrical Metrology that controls high k plus interface Void detection in copper Lines Killer Pores in low k Sidewall barrier layer control below seed Cu

7. International Technology Roadmap for Semiconductors Difficult Challenges before 65 nm / 2007 Factory level and company-wide metrology integration Impurity detection (especially particles) at levels of interest for starting materials & reduced edge exclusion for metrology tools. Control of high-aspect ratio technologies such as Damascene challenges all metrology methods. Key requirements are void detection in copper lines and pore size distribution in patterned low k. Measurement of complex material stacks and interfacial properties including physical and electrical properties. Measurement test structures and reference materials.

8. International Technology Roadmap for Semiconductors Difficult Challenges after 65 nm / 2007 Nondestructive, production worthy wafer and mask level microscopy for critical dimension measurement for 3-D structures, overlay, defect detection, and analysis. Standard electrical test methods for reliability of new materials, such as ultra-thin gate and capacitor dielectric materials, are not available. Statistical limits of sub-65 nm process control. 3D dopant profiling. Determination of manufacturing Metrology when device and interconnect technology remain undefined.

9. International Technology Roadmap for Semiconductors GAPS in Litho Metrology Precision of CD-SEM Proof of 3D CD for Tilt Beam CD-SEM Commercialization of 3D software for top-down CD-SEM Depth of Field Issues for CD-SEM Reference Materials for 65 nm node and below Standard method for Precision of Discrete CD Library Probe Tip Technology for CD-AFM

10. International Technology Roadmap for Semiconductors Changes to Lithography Metrology Accelerated MPU Gate Length dilutes advances in CD Measurement –Will 15% Process 3 be adopted?? Addition of Line Edge Roughness Metrics Overlay may face difficulties associated with mixing exposure tools –e.g., 2 different 157 nm exposure tools for via & metal trench (or 157 nm for lines & Electron Projection for Via)

11. International Technology Roadmap for Semiconductors Line Edge Roughness Requirements Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi Line Edge Roughness Correlated to Leakage Current Increase Patterson, et. al., SPIE 2001 AVE CD = 150 nm

12. International Technology Roadmap for Semiconductors Why are CD Measurement Requirements RED? There is no universal metrology solution for all CD measurements. –e.g., Scatterometry meets Focus-Exposure precision needs to (70 nm node?) for resist lines but not for contacts (yet). –Can Scatterometry measure LER ? 3D info needed for undercut gate, contact, and other structures. Precision includes tool matching and near + long term measurement variation.

13. International Technology Roadmap for Semiconductors Gaps in FEP Metrology Physical Metrology for high k gate stack –Optical Models for next High k (beyond ZrO2 and HfO2) –Commercial availability of high k optical model in software –Interfacial control for interface between high k and silicon Electrical Metrology for high k gate stack –Application of Non-contact C-V to next High k (beyond ZrO2 and HfO2) –Comparison of non-contact electrical to C-V –USJ Metrology Ultra Shallow Junction Metrology (USJ) –Dose/Junction Control –2D Dopant Profiling with spatial resolution Metrology for post CMOS –SOI ; SiGe ; Vertical Transistors

14. International Technology Roadmap for Semiconductors FEP Metrology Optical and Electrical measurement of High can be done for development but needs to be robust for manufacturing Metrology for interface below High needs R&D USJ Metrology needs development for < 65 nm FERAM needs fatigue testing for 10 16 read/write cycles

15. International Technology Roadmap for Semiconductors Gaps in Interconnect Metrology VOID Detection in Copper lines Killer Pore Detection in Low Barrier / Seed Cu on sidewalls Control of each new Low

16. International Technology Roadmap for Semiconductors Interconnect Metrology Random isolated void detection (size of 25% of line width) at < 1% in copper lines may not be measurable in-line Max Low Pore size of 5% of line width Metrology for electrochemical deposition will be included in Metrology Roadmap

17. International Technology Roadmap for Semiconductors Materials Characterization Enables Process and Metrology Development Short term: New Aberration Corrected Lens for STEM/TEM Long Term: Atom Probe Dave Muller - Lucent

18. International Technology Roadmap for Semiconductors 2001 Grand Challenges Development of Metrology tools in time. Rapid non-destructive metrology for CD, overlay, defect detection and line edge roughness that meets ITRS timing and technology requirements.

19. International Technology Roadmap for Semiconductors Will Market Risks allow for innovation?

20. International Technology Roadmap for Semiconductors US TWG Writing Team Peter Borden (Boxer-Cross)FEP Murray Bullis (SEMI)Intro Alain Diebold (Int. SEMATECH)Intro/Edit Jack Martinez (NIST) Standards Cecilia Martner (Applied Materials)Interconnect Clive HayzeldenFEP Dick Hockett (CEA/PHI Metrics)Materials Char. Steve Knight (NIST)Statistical Limits Noel Poduje (ADE)FEP Michael Postek (NIST)Microscopy Brad van Eck (Int. SEMATECH)Int. Meterology Andras VladarMicroscopy

21. International Technology Roadmap for Semiconductors Backup

22. International Technology Roadmap for Semiconductors New Metrology Need: Standardized Statistics for Discretized Data Some new methods fit measurement to a discrete set of possible results This could result in artificially good precision values that do not really evaluate process control capability

23. International Technology Roadmap for Semiconductors 2001 Metrology Requirements Summary

24. International Technology Roadmap for Semiconductors S L e.g. 150 nm lines 300 nm pitch Novel Methods for FEM control Optical CD using Overlay System Automatic cross- sectioning, imaging and metrology from all sites of the FEM Dose Focus Dualbeam FIB FEI

25. International Technology Roadmap for Semiconductors Leakage Current correlated to Line Edge Roughness Center of data at 150 nm channel length with drive current of 500 A/ m Leakage plotted versus active width of transistor The two lines show the dependence for the case of low and high line edge roughness. Units for leakage current are A/ m, plotted on a logrithimic scale Patterson, et. al., SPIE 2001 Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi

26. International Technology Roadmap for Semiconductors CD-SEM a Potential Solution for Wafer and Mask / R&D + Production Sato and Mizuno, EIPBN 2000, Palm Springs, CA Barriers and Solutions 193 & 157 nm Resist Damage » lower dose images Lineshape » tilt beam SEM vs software Precision Improvements » new nano-tip source Depth of Focus » new SEM concept needed Ultimate Limit of CD-SEM » ~ 5 nm for etched poly Si Gate

27. International Technology Roadmap for Semiconductors Interconnect Metrology Solutions Barrier/Seed Cu Films 5 Potential Solutions all expected to meet precision requirements some are extendable to patterned wafers Acoustic ISTS Picosecond acoustics X-ray reflectivity X-ray fluorescence Non-contact resistivity

28. International Technology Roadmap for Semiconductors Voids in Copper Pore Size/Killer Pores in Low k Random isolated void detection in copper lines may be used in development at levels above the < 1% metric <1% may not be measurable

29. International Technology Roadmap for Semiconductors Metrology & New Structures Gate Drain Source Vertical Transistor