1. Metrology Roadmap 2003 Update EuropeUlrich Mantz (Infineon) Mauro Vasconi (ST) JapanMasahiko Ikeno (Mitsubishi) Toshihiko Osada (Fujitsu) Akira Okamoto (SONY) KoreaTaiwan USSteve Knight (NIST) Alain Diebold (Int. SEMATECH)

2. Difficult Challenges 5 nm, Through 2009 5 nm, Through 2009 Starting materials metrology and manufacting metrology are impacted by the introduction of new substrates such as SOI. Impurity detection (especially particles) at levels of interest for starting materials and reduced edge exclusion for metrology tools. CD, film thickness, and defect detection are impacted by thin SOI optical properties and charging by electron and ion beams. < 45 nm, Beyond 2009 New strategy for in-die metrology must reflect across chip and across wafer variation. Structural and elemental analysis at device dimensions.

3. Questions for Litho TWG What are requirements for on-trac control –Feed – forward control? Feed-back control? –Which parameters? CD Macro-inspection Overlay –What is controlled? Focus or dose? Resist thickness? LER and LWR definitions Opinion on new overlay targets?

4. Questions for FEP metrology Will compositional control really be used during manufacturing? What structural information is needed for etch control?

5. Questions for Interconnect metrology Since voids are also a reliability issue, is void detection after metal deposition critical? Are texture measurements for seed layers critical?