2. Contents Introduction(Chapter 1)Introduction(Chapter 1) Logic Synthesis for Low Poser(Chapter 6)Logic Synthesis for Low Poser(Chapter 6) Low Power Arithimetic Components(Chapter 7)Low Power Arithimetic Components(Chapter 7) Low Power Microprocessor Design(Chapter 9)Low Power Microprocessor Design(Chapter 9) Algorithm and Architectural Level MethodologiesAlgorithm and Architectural Level Methodologies (Chapter 11) (Chapter 11) Low Power Clock Distribution(Chapter 5)Low Power Clock Distribution(Chapter 5) Portable Video-on-Demand in Wireless Communication(Chapter 10)Portable Video-on-Demand in Wireless Communication(Chapter 10)

3. INTRODUCTION(CHAPTER 1) 1.1 Motivation 1.2 Sources of Dissipation in Digital Integrated Circuits 1.3 Degrees of Freedom 1.4 Recurring Themes in Low-Power 1.5 Emerging Low Power Approaches 1.6 Summary

4. 1.1 Motivation[1] Traditional system performanceTraditional system performance - Synonymous with circuit speed or processing power - Synonymous with circuit speed or processing power - MIPS or MFLOPS - MIPS or MFLOPS - Direct correspondence between silicon area and cost - Direct correspondence between silicon area and cost - Increasing the implementation area - Increasing the implementation area -> higher packaging costs as well as reduced fabrication yield -> higher packaging costs as well as reduced fabrication yield -> increased product cost -> increased product cost - Improvements in system performance - Improvements in system performance -> the expense of silicon real estate -> the expense of silicon real estate - Until recently, power considerations were only secondary - Until recently, power considerations were only secondary concern concern

5. 1.1 Motivation[2] Recent Design trendRecent Design trend - Remarkable success and growth of the portable consumer - Remarkable success and growth of the portable consumer electronics market electronics market - Lap-top computers, Personal Digital Assistants, Cellular - Lap-top computers, Personal Digital Assistants, Cellular phones, Pagers, MP3, and other portable devices phones, Pagers, MP3, and other portable devices -> Average power consumption has become a critical design -> Average power consumption has become a critical design concern concern

6. 1.1 Motivation[3] Future portable multi-media terminalFuture portable multi-media terminal - supports high bandwidth wireless communication, bi-directional motion video, high quality audio, speech and pen-based input and full texts/graphics - supports high bandwidth wireless communication, bi-directional motion video, high quality audio, speech and pen-based input and full texts/graphics -> Projected power budget: 40W -> Projected power budget: 40W -> Nickel-Cadmium battery offers around 20 Watt-hours/pound -> Nickel-Cadmium battery offers around 20 Watt-hours/pound -> 20 pounds of batteries for 10 hours of operation -> 20 pounds of batteries for 10 hours of operation -> Nickel-Metal-Hydride offers around 30-35 Watt-hours/pound -> Nickel-Metal-Hydride offers around 30-35 Watt-hours/pound -> 7 pounds -> 7 pounds - Battery capacity has improved with a factor 2 to 4 over 30 years - Battery capacity has improved with a factor 2 to 4 over 30 years - Rechageable lithium or polymers is anticipated to increase battery life-time with no more than 30 to 40% around year 2000 - Rechageable lithium or polymers is anticipated to increase battery life-time with no more than 30 to 40% around year 2000

7. 1.1 Motivation[4] - In absence of low-power design techniques, current and - In absence of low-power design techniques, current and future portable devices will suffer from either very short battery future portable devices will suffer from either very short battery life or unreasonable heavy battery packs life or unreasonable heavy battery packs -> A low power design approach should be adopted -> A low power design approach should be adopted Trend in microprocessor power comsumptionTrend in microprocessor power comsumption - a function of die area x clock frequency - a function of die area x clock frequency - P = α · area · f clock with α = 0.063 W/cm 2 · MHz - P = α · area · f clock with α = 0.063 W/cm 2 · MHz - 10 cm2 microprocessor clocked at 500 MHz would consume - 10 cm2 microprocessor clocked at 500 MHz would consume 315 Watt 315 Watt -> increasingly expensive packaging and cooling strategies -> increasingly expensive packaging and cooling strategies -> chip power consumption increases -> chip power consumption increases

8. 1.1 Motivation[5] Issue of reliabilityIssue of reliability - High power systems tend to run hot - High power systems tend to run hot -> high temperature tends to exacerbate several silicon failure -> high temperature tends to exacerbate several silicon failure mechanism mechanism - Every 10 °C increase in operating temperature doubles a component’s failure rate - Every 10 °C increase in operating temperature doubles a component’s failure rate -> Thermal runaway, gate dielectric, junction fatigue, -> Thermal runaway, gate dielectric, junction fatigue, electromigration diffusion, electrical-parameter shift, package- electromigration diffusion, electrical-parameter shift, package- related failure, silicon-interconnect fatigue related failure, silicon-interconnect fatigue

9. 1.1 Motivation[6] Application considerationApplication consideration - Pace makers and digital watches - Pace makers and digital watches -> minimize power to an absolute minimum -> minimize power to an absolute minimum -> Overall power levels are normally below 1 mW -> Overall power levels are normally below 1 mW - Cellular phones and portable computers - Cellular phones and portable computers -> keep the battery lifetime reasonable and packaging cheap -> keep the battery lifetime reasonable and packaging cheap -> Power levels below 2 W -> Power levels below 2 W - Workstations and set-top computers - Workstations and set-top computers -> reduce system cost(cooling, packaging, energy bill -> reduce system cost(cooling, packaging, energy bill

10. 1.2 Sources of Dissipation in Digital ICs Static PowerStatic Power - Ideal CMOS circuits dissipate no static (DC) power in the - Ideal CMOS circuits dissipate no static (DC) power in the steady state steady state - In reality, there are leakage currents and substrate injection - In reality, there are leakage currents and substrate injection currents currents -> give rise to a static component of CMOS power dissipation -> give rise to a static component of CMOS power dissipation - Static component of power consumption in low-power CMOS - Static component of power consumption in low-power CMOS should be negligible should be negligible - Focus shifts primarily to dynamic power consumption - Focus shifts primarily to dynamic power consumption

11. 1.2 Sources of Dissipation in Digital ICs Dynamic PowerDynamic Power - dynamic component of power dissipation arises from the - dynamic component of power dissipation arises from the transient switching behavior of the CMOS device transient switching behavior of the CMOS device - At some point during the switching transient, both the NMOS - At some point during the switching transient, both the NMOS and PMOS devices will be turned on and PMOS devices will be turned on -> a short-circuit exists Vdd and ground and currents flows -> a short-circuit exists Vdd and ground and currents flows -> 10-15% of the total power -> 10-15% of the total power - Capacitance charging consumes most of the power by CMOS - Capacitance charging consumes most of the power by CMOS - CMOS power consumption depends on the switching activity - CMOS power consumption depends on the switching activity of signals involved of signals involved

12. 1.2 Sources of Dissipation in Digital ICs Dynamic PowerDynamic Power - Average CMOS power consumption - Average CMOS power consumption Pdyn = α C V 2 dd f Pdyn = α C V 2 dd f - Dynamic power is proportional to switching activity, capacitive - Dynamic power is proportional to switching activity, capacitive loading, and the square of the supply voltage loading, and the square of the supply voltage - In CMOS, 90% of the total power dissipation - In CMOS, 90% of the total power dissipation

13. 1.3 Degree of Freedom[1] Three degree of freedom inherent in the low-power design spaceThree degree of freedom inherent in the low-power design space - Voltage - Voltage - Physical capacitance - Physical capacitance - Activity - Activity - Reduce one or more of these factors - Reduce one or more of these factors - These parameters are not completely orthogonal and - These parameters are not completely orthogonal and can not be optimized independently can not be optimized independently

14. 1.3 Degree of Freedom[2] 1.3.1 Voltage1.3.1 Voltage - Most direct and dramatic means of minimizing energy - Most direct and dramatic means of minimizing energy comsumption comsumption - Figure 1.6 - Figure 1.6 -> Energy consumption vs. Supply voltage -> Energy consumption vs. Supply voltage -> Circuit delay vs. Supply voltage -> Circuit delay vs. Supply voltage - Designer sacrifice increased physical capacitance or - Designer sacrifice increased physical capacitance or circuit activity for reduced voltage circuit activity for reduced voltage - Performance requirement & Compatibility - Performance requirement & Compatibility -> Primary derterming factor -> Primary derterming factor

15. 1.3 Degree of Freedom[3] As supply voltage is loweredAs supply voltage is lowered - Circuit delays increase (Figure 1.6b) - Circuit delays increase (Figure 1.6b) -> Reduce system performance -> Reduce system performance - In order to meet system performance requirements, - In order to meet system performance requirements, these delay increases must be checked these delay increases must be checked - Some techniques must be applied - Some techniques must be applied -> Technological or architectural compensation -> Technological or architectural compensation - Limit of the advantageous range of voltage supply - Limit of the advantageous range of voltage supply V dd ≈ V t V dd ≈ V t

16. 1.3 Degree of Freedom[4] Issue of Compatibility and Inter-operabilityIssue of Compatibility and Inter-operability - Most off-the-shelf components operate off either 5V, - Most off-the-shelf components operate off either 5V, 3.3V or, more recently less than 3V supply 3.3V or, more recently less than 3V supply - Communications are required with components operating - Communications are required with components operating at a standard voltage at a standard voltage - This dilema can be lessened by the availability of - This dilema can be lessened by the availability of DC-DC level converters -> More cost DC-DC level converters -> More cost - System operates off a single low voltage (e.g 2V t ) - System operates off a single low voltage (e.g 2V t ) -> level shifting only required for communication -> level shifting only required for communication with the outside world with the outside world

17. 1.3 Degree of Freedom[5] 1.3.2 Physical Capacitance1.3.2 Physical Capacitance - Power consumption depends linearly on the physical - Power consumption depends linearly on the physical capacitance being switched. capacitance being switched. - Factors contributing to the physical capacitance of - Factors contributing to the physical capacitance of a circuit a circuit - Two primary sources of capacitance in CMOS - Two primary sources of capacitance in CMOS -> Devices and Interconnect -> Devices and Interconnect

18. 1.3 Degree of Freedom[6] 1.3.2 How to keep the capacitance at a minimum1.3.2 How to keep the capacitance at a minimum - Use less logic, smaller devices, fewer and shorter - Use less logic, smaller devices, fewer and shorter wires wires Techniques for reducing the active areaTechniques for reducing the active area - resource sharing - resource sharing - logic minimization - logic minimization - gate sizing - gate sizing

19. 1.3 Degree of Freedom[7] Techniques for reducing the interconnectTechniques for reducing the interconnect - register sharing - register sharing - common sub-function extraction - common sub-function extraction - placement and routing - placement and routing Reducing device sizesReducing device sizes -> Reduce physical capacitance -> Reduce physical capacitance -> but also reduce the current drive of the transistors -> but also reduce the current drive of the transistors -> cause the circuits to operate more slowly -> cause the circuits to operate more slowly -> prevents us from lowering V dd as much as we might -> prevents us from lowering V dd as much as we might otherwise be able to do otherwise be able to do

20. 1.3 Degree of Freedom[8] Increase in physical interconnect capacitanceIncrease in physical interconnect capacitance -> Reduce significantly voltage and/or activity -> Reduce significantly voltage and/or activity -> this may result in a net decrease in power -> this may result in a net decrease in power Low power design is a joint optimization process in which the variables cannot be manipulated independentlyLow power design is a joint optimization process in which the variables cannot be manipulated independently

21. 1.3 Degree of Freedom[9] 1.3.3 Activity1.3.3 Activity - Even if a chip contains a huge amount of physical - Even if a chip contains a huge amount of physical capacitance, no dynamic power will be consumed capacitance, no dynamic power will be consumed without switching without switching Two key components to switching activityTwo key components to switching activity 1) Data rate, f 1) Data rate, f -> in synchronous systems, f might correspond to -> in synchronous systems, f might correspond to the clock frequency the clock frequency 2) Data activity, α 2) Data activity, α - Average periodicity of data arrivals - Average periodicity of data arrivals - depends on the switching activities, logic functions, - depends on the switching activities, logic functions, and spatial and temporal correlations among the circuit input and spatial and temporal correlations among the circuit input

22. 1.3 Degree of Freedom[10] 3) Glitching 3) Glitching - Spurious and unwanted transitions that occur before - Spurious and unwanted transitions that occur before a node settle down to its final steady-state value a node settle down to its final steady-state value Effective Physical capacitance C effEffective Physical capacitance C eff C eff = α C C eff = α C - Power Consumption by a CMOS circuit: P - Power Consumption by a CMOS circuit: P P = αCV 2 f = C eff V 2 f P = αCV 2 f = C eff V 2 f - Reducing switching activity in FSM - Reducing switching activity in FSM -> power conscious state encoding[25], multi-level -> power conscious state encoding[25], multi-level logic optimization logic optimization - Data representation - Data representation -> Sign magnitude representation vs. Two’s comprement representation -> Sign magnitude representation vs. Two’s comprement representation -> Activity vs. computation complexity -> Activity vs. computation complexity

23. 1.4 Recurring Themes in Low-Power[1] Four principle themesFour principle themes - Trading area-performance for power - Trading area-performance for power - Adapting designs to environmental conditions or data structure - Adapting designs to environmental conditions or data structure - Avoiding waste - Avoiding waste - Exploiting locality - Exploiting locality Trding area-performance for powerTrding area-performance for power - The most important theme - The most important theme - Power can be reduced by decreasing the system supply - Power can be reduced by decreasing the system supply voltage and allowing the performance of the system to voltage and allowing the performance of the system to degrade degrade

24. 1.4 Recurring Themes in Low-Power[2] - If the system designer is not willing to give up the performance - If the system designer is not willing to give up the performance -> consider applying techniques such as parallel processing -> consider applying techniques such as parallel processing to maintain perfornance at low voltage to maintain perfornance at low voltage -> These techniques may incur an area penalty -> These techniques may incur an area penalty Adapting design to environmental conditionsAdapting design to environmental conditions - Dynamically change operation of the circuits as the - Dynamically change operation of the circuits as the characteristics of the environmental and/or the statistics of the characteristics of the environmental and/or the statistics of the input streams vary input streams vary

25. 1.4 Recurring Themes in Low-Power[3] -> Choosing the most economic communication medium and -> Choosing the most economic communication medium and changing error recovery and encoding to suit the channel changing error recovery and encoding to suit the channel noise and error tolerence noise and error tolerence -> Selectively precompute the output logic values of the -> Selectively precompute the output logic values of the cuircuits one clock cycle before they are required cuircuits one clock cycle before they are required -> And then, use the precomputed values to reduce internal -> And then, use the precomputed values to reduce internal switching activity in the succeeding clock cycle switching activity in the succeeding clock cycle

26. 1.4 Recurring Themes in Low-Power[4] Avoiding wasteAvoiding waste - Clock modules when they are idle - Clock modules when they are idle - Glitching - Glitching -> avoid by path balancing and choice of logic family -> avoid by path balancing and choice of logic family - Use dedicated rather than programmable hardware - Use dedicated rather than programmable hardware - Reduce control overhead by using regular algorithms and - Reduce control overhead by using regular algorithms and architecture architecture - Take the form of designing system to meet rather than surpass - Take the form of designing system to meet rather than surpass performance requirements performance requirements

27. 1.4 Recurring Themes in Low-Power[5] Exploiting localityExploiting locality - Grobal operations inherently consume a lot of power - Grobal operations inherently consume a lot of power - Data transferring - Data transferring -> at expense of swithing a large bus capacitance -> at expense of swithing a large bus capacitance - Design partitioned to exploit locality of reference - Design partitioned to exploit locality of reference -> minimize the amount of expensive global communications -> minimize the amount of expensive global communications employed in favor of much less costly local interconnect employed in favor of much less costly local interconnect networks networks -> Especially for DSP applications -> Especially for DSP applications

28. 1.5 Emerging Low Power Approaches[1] Low power digital design requires optimization at all levels of the design hierachyLow power digital design requires optimization at all levels of the design hierachy - techonology, devices, circuits, logics, architecture, - techonology, devices, circuits, logics, architecture, and system level[Figure 1.8] and system level[Figure 1.8] The goal of this book is to give a comprehensive overview of the different approaches that are currently being conceived at the various levels of design abstractionThe goal of this book is to give a comprehensive overview of the different approaches that are currently being conceived at the various levels of design abstraction The techniques and approaches ultimately all come down to a fundamental set of concepts: dissipation is reduced by lowering either the supply voltage, the voltage swing, the physical capacitace, the swithing activity or a combination of the aboveThe techniques and approaches ultimately all come down to a fundamental set of concepts: dissipation is reduced by lowering either the supply voltage, the voltage swing, the physical capacitace, the swithing activity or a combination of the above

29. 1.5 Emerging Low Power Approaches[2] System: Patitioning, Power-down, Power statesSystem: Patitioning, Power-down, Power states Algorithm: Complexity, Concurrency, Regularity,Algorithm: Complexity, Concurrency, Regularity, Locality Locality Architecture: Paralleism, Pipelining, Redundancy,Architecture: Paralleism, Pipelining, Redundancy, Data encoding Data encoding Circuit/Logic: Logic styles + manipulation,Circuit/Logic: Logic styles + manipulation, Transistor sizing, Energy recovery Transistor sizing, Energy recovery Technology: Threshold reduction,Technology: Threshold reduction, Double-threshold devices Double-threshold devices

30. 1.6 Summary[1] A low voltage/low threshold technology and circuit approachA low voltage/low threshold technology and circuit approach Low power interconnectLow power interconnect Low-power system synchronization approachesLow-power system synchronization approaches Dynamic power management techniquesDynamic power management techniques Application specific processingApplication specific processing A conscientious drive towards parallel and distributed computingA conscientious drive towards parallel and distributed computing A system-level approach towards power minimizationA system-level approach towards power minimization An integrated design methodology including synthesis and compilation toolsAn integrated design methodology including synthesis and compilation tools