1. EMCal project TRU (Trigger Region Unit) status Sept ‘08 1 Norbert Novitzky 9/14/2015

2. Outline EmCal – General overview Trigger – Requirements ( design goals, key parameters ): – Schematics ( tower to CTP ) Trigger mapping TRU board Trigger in TRU L0 latency STU board Hierarchical trigger fro EMCal Our participation Status – Tests, what are done – Remaining tasks – Time schedule Future activities 29/14/2015

3. 3 AcceptanceEMCalPHOS  110°100°  1.40.24 R interaction 4.3m4.6m 1/3 super module: 48x8 (384) towers. CharacteristicValue Moliere radius3.2cm # Towers12672 Ambient temperature18° Light yield (APD)3.3e/MeV Preamplifiers1V/pC, 15ns Shaper200ns, G-2 Dynamic lin. Range14 bit Led-scintillator Back plate Opt. fibers EMCal in ALICE 1 (super) moduleEMCalPHOS Modules105 Towers11523584 FEE36112 TRU38 STU/TOR (for all modules) 11 Tables are showing general information about the EMCal detector in ALICE. Because of the similarities with PHOS detector, some information are compared with the PHOS detector. 9/14/2015

4. 4 12x FEE 12x FEE TRU 12x FEE 12x FEE TRU 12x FEE 12x FEE TRU STU CTP (central trigger processor) CTP (central trigger processor) RCU t=0 [collision] 2x2 data 135ns L0 signal 600ns L0 800ns L0 from CTP 1200ns Start of data 1400ns Data End of data 1915ns L1 6200ns Other L0 detectors L1 calculation The EMCAL will provide L0 and L1 trigger signals. The L0 must be provided within 800ns to CTP, where it is decided with other detectors. The main calculation for L0 is don in TRU level. The L1 is decided in STU. It is more complicated calculation, but first it is needed to transfer the data from TRUs. This procedure start only when the system receive the L0 from CTP (via RCU boards). 29xTRU

5. STU Max 12 m CTP Vo multiplicity LTU TTC High-speed link Ethernet cable Max 12 m 1 Super module TRU Level-0 Level-1-L Level-1-M Level-1-H JET 5 Level-1 global decisions in STU f(nxn) RCUDAQ HLT Level-0 local-decisions in TRU (4x4)> x 16 x TRU 192 x FEE TRU Fake Altro trigger data High-speed link Ethernet cable This figure shows the path for L0 and L1 trigger signals from super modules to the CTP (central trigger processor) The L0 is generated in TRU (Trigger Region Unit) The L1 is generated in STU (Summary Trigger Unit) 9/14/20155

6. 1 FEE 8 x (2x2) 100 ns 1 FEE 8 x (2x2) 100 ns 1 FEE 8 x (2x2) 100 ns 96 ADC 12 bit @40MHz FPGA Virtex-5 4x4 groups 1 TRU = Analogue FOR cables from 12 FEE Level-0 RCU TRU Trigger region 8 x 48 towers = 384 8 x 12 (2x2) = 96 signals 1 TRU =12 FEE = 1 SM in z 1 FEE card: 32 APD in 8 towers 8 x analogue OR 2x2 CSP numbering Level-1 High pT Level-1 JET STU Summary Trigger 96 (2x2) FPGA Virtex-5 0 1515 7 24 23 16 8 3131  z 8 x (2x2) analogue 1 RCU branch A 1 RCU branch B 1 RCU partition: 48 x 8 towers 1..9 10,11,12 1x STU32 x TRU384 x FEE 1 FEE = 32 inputs, 8 output for TRU Towers ~5-30cm Max ~12m 2x2 In this figure we can follow the signal from towers in super module, through the front-end electronics, TRU module until it reach the STU. 9/14/20156

7. 7 Power regulators Inputs from FEE – 112 channels (but only 96 will be in use) LVDS bus GTL bus Prom LVDS control High speed link (to STU) TRU board 10 Test pins 9/14/2015

8. Trigger (TRU) 8 Hierarchy of the trigger in EMCal: The 2x2 sum of the towers from FEE->TRU (112 channels as input in one TRU) In TRU we create an other 2x2 sum of input channels, what mean now we have 4x4 sum for towers. Then we apply a digital threshold. (69 groups) The data from TRUs go to STU.  L0: create an OR from every TRU (quick process)  L1 : more complicated, using every TRU data, but it is done in STU 2x2 1 Tower 2x2 = 1 TRU chan. 4x4 for trigger L0800 ns L1 6.2  s L2 88  s Requirements 9/14/2015

9. Bx t=0 Convert the incoming signal to a digital signal (12 bit) 170ns CTP max. 800 ns ~ 35 m = 154 ns Xilinx Virtex-5 40 MHz 345 ns 40 MHz 20 MHz NRZ Trigger TRU 135 ns 580 ns FEE ADC 305 ns 640 ns Level-0 Algorithm Maximum time for calculation 235 ns STU 600ns ~ 5 m = 22 ns 69 parallel processes Reading the data, analog sum (2x2) De-serialize the data ProcessTime Data in FEE135ns ADC process170ns De-serialize40ns L0 Algorithm in TRU235ns STU calculation (for L0)40ns Cables~178ns Every 4x4 calculation will run in parallel processes in the FPGA. It creates the 4x4 group and check, if the energy reach a certain threshold or not. Every 4x4 group can have different threshold. The limit to reach the CTP is 800ns. The table shows, how much time is needed to the sub-processes and how much time is left for the calculation 9/14/20159

10. DCS interface TTCRq V0 interface DDL interface L0 in 4 TRU inputs 32 TRU inputs 4 TRU inputs Trigger outputs T0-B1 T2-B3 T38-B39 T36-B37 T34-B35T32-B33T30-B31 T28-B29T26-B27 T24-B25 T22-B23T20-B21T18-B19 T16-B17 T14-B15 T12-B13 T10-B11 T8-B9 T6-B7T4-B5 T0-B1 = Top is input 0, Bottom is input 1 STU (Summary Trigger Unit) 9/14/201510

11. STU 11 The STU has 40 input (for EMCal we will use 32) of high-speed link. The board also contain an FPGA (Virtex-5, same what we have on TRU) For generating the L0 signal it will create an OR from every TRU. If one has an L0 signal, then it will send it to CTP. After that it will create also a L1 trigger signal : L1 Gamma (is the same procedure, like in TRU 4x4 regions) Low pT jets Medium pT jets High pT jets Numbers are the readout order and not the ADC channel number Total: 204 subregions Below subregion delimitation, 4x4 fast OR  8x8=64 towers 9/14/2015

12. FPGA program (basic) 12 There are two main languages in use: VHDL and Verilog The basic component of the program is the CLOCK. Every calculation, every signal is based on this clock. (in TRU it is a 40MHz clock, or we will use the LHC clock ~40.08 MHz) The next is to match the pinout map with the correct chip pins. Every FPGA has different pinout map (we are using Xilinx Virtex-5 LX110 BGA1153). After that the compilation can find the correct way. If you miss the pin, you will not get anything. The pinouts for our FPGA (what is in use) 9/14/2015

13. FPGA program (basic) 13 The start of the program is definition of the ports. We need to define the signal, what we will use: IN or OUT signal The signal is std_logic (standard logic). We can also define it as a vector State mashine A very useful tool in hardware language. Here as a very simple example is a street-light. 9/14/2015

14. Our participation in TRU 14 1.The production of 38 TRU boards. (including 2 prototypes) 1.First test of the TRU prototypes before the full production. (Dong, Jo, Hans, Norbert) a)First power up b)Start to program the FPGA (also Prom) c)Test pattern for ADCs d)Test of High speed link and LVDS control (with Olivier) e)2 remaining problem before full production: I.GTL bus communication II.Actel refreshing (not necessary) 9/14/2015

15. Test, what we had done 15 First power up of the board (Problem 1)(Problem 1)  All of the starting problems was solved The power regulators gave the right values (Problem 2)(Problem 2)  Some small changes must be made Programming the FPGA via Xilinx cable: (Problem 3)(Problem 3)  Directly – tested  From the flash (prom): 1.Serial programming (~15 seconds) 2.Parallel programming (~2-3 seconds) The test pins are working fine, the LEDs are also ok. Fake Altro test  The readout of the trigger data with the GTL bus Conclusion The design of the TRU board is good, there is no need to change it. Ready for full production. 9/14/2015

16. Test of ADCs 16 The ADCs do the conversion from analog signal to digital (12 bit) signal. After that the FPGA can handle the data. The ADC is working with 40MHz, it can sample the incoming data every 25ns. After that it provides 12 bit digital signal from data. Sampling points (every 25ns) 40MHz – frame clock It’s the start and end of the data. 240 MHz clock – data clock In every rising and falling edge is one bit 9/14/2015

17. 17 40MHz clock – frame clock 240MHz clock – data clock ADCs 8 channels = 1 chip Deskew test pattern data First thing to do: test the ADCs(12 bits in 8 channels) The part of the program initializes all the ADCs. You need to write to register few data to initialize the completely. After that we setup the test patterns: Sync: 101010101010 (~240MHz clock) Deskew: 111111000000 (~40MHz clock) First the testing of the FPGA features. For testing we can use: Logic Analyzer (10 test pins = 10 channels) ChipScope – built-in logic analyzer inside FPGA Test of ADCs 9/14/2015

18. TRU-STU test First test with slow control: (2 inputs, 2 outputs links) We had to solve some issues with the correct pins in FPGA. We solved it. As far as I understood, it will be not used in final setup. They want to use the black-plane to operate with the board. Second test was the high-speed link. (1 input (40MHz clock from STU, later the LHC clock), 3 output links) We were sending 450 words in packet, instead of 96. We solved also some last- minute issues with program. 4 inputs on STU were tested, worked properly. For further test more time is needed: Test all inputs (compilation time increases) Test with few TRU at once. (synchronization) 189/14/2015

19. Short term plan Actel refresh – it protects the FPGA from SUE (single upset events)  Dong is working on that now  This test will be good to be done, but not necessary. Long term plan After full test of the prototype, we need to start the full production. Ordering the missing parts, sending it to the companies. Further test with STU-TRU setup. Writing the final FPGA code for the trigger (with Jo, and maybe Dong) 199/14/2015

20. Orders 20 Resistors and capacitors:~1000 CHF Connectors:~1000 CHF Chips:~2000 CHF ADCs: SILICA AVNET (FR):23'964 CHFdelivery: about 16/02/09 AVNET EMG (CH):24’311 CHFdelivery: about 09/02/09 DIGI-KEY (US):33’538 CHFdelivery: from stock (to be checked before ordering) SPOERLE (CH):34’730 CHFdelivery: within 12 weeks (about 12/02/09) After the components we need to order the boards (2 are already at Cern), and the mounting. This I don’t know how much will cost. 9/14/2015

21. Backup 219/14/2015

22. First power up of board (Problem 1) The power supply values needed (INPUT values): 4.0V @ 3.3 A 4.2V @ 3.5 A 3.3V @ 3.0 A At first power up we discovered a capacitor (C126) was mounted inversed and making to short circuit. The silk screen shows the plus sign on the wrong side. To be corrected in the mounting files. If we are not using the backplane, to turn on the board we need to put a jumper on ST1. 229/14/2015

23. Testing the volgates (Problem 2) The Q2 must be corrected: The TPS74410 is switched to TPS74401 The R68 and R64 must be switched The C222 need to be changed to 100pF The bias pin 6 should be connected to 3.3V IC32: Same TPS7701 R81 and R80 must be switched The pin 6 should be connected to 3.3V The C227 need to be changed to 100pF On the board there are several voltage regulators: Digital Power Q2 – 1.0V output Q1 – 2.5V output IC33 – 3.3V output Q3 – 2.5V output Reg1 –2.5V output ADC powers (must be enable from FPGA): IC31 – 3.3V output IC32 – 1.8V output 239/14/2015

24. More setup for TRUs (Problem 3) There are several options how to use the TRU. The main switch for programming the FPGA is the SW1: Here the R242 and R241 should be removed. This switch determine how should be the FPGA programmed (Prom – parallel or serial, Actel…) The configuration on silkscreen is not correct for the parallel programming. 249/14/2015

25. Programming the FPGA (Problem 3) The R124 must be removed to be able to program the FPGA from PROM or ACTEL. It is an active low signal, should be connected to the ground The R71 must be removed for Actel programming (not yet tried) To program the FPGA from PROM: Remove the R22 (C240 is not needed) To disable the clock CLKOUT R18 must be removed. 259/14/2015