1. SDR Test bench Architecture WINLAB – Rutgers University Date : October 15 2009 Authors : Prasanthi Maddala, prasanthi.m@gmail.comprasanthi.m@gmail.com Khanh Le, kle@winlab.rutgers.edukle@winlab.rutgers.edu

2. SDR Test Bench 2 SDR platform – V1.0 The Figure above shows the first version of SDR platform and this document describes a test bench being developed for it.

3. SDR Test Bench 3 This Figure shows a test bench for an SDR design. The test bench could contain different drivers and monitors controlled by the simulation manager as shown in the figure, depending on the design under test. Our current version of test bench provides an Ethernet driver, a DiBo SPI monitor, a WiBo control monitor, and a simulation manager that interacts with these blocks.

4. SDR Test Bench 4 Ethernet Driver Ethernet driver emulates the Ethernet receive PHY.

5. SDR Test Bench 5 Ethernet Driver On receiving a signal from the simulation manager along with the data to be sent, Etherner driver sends data to the receive Ethernet interface in the SDR design. It can be either set to 100 Mbps or 1Gbps through the generic DATA_RATE It can also add Ethernet and IP headers, or Ethernet header alone (depending on the signal add_hdr), before sending out data to the design under test.

6. SDR Test Bench 6 Ethernet Driver – SDR Design Interface Signal NameIn/OutWidthDescription eth_data_validOut1Active High. Indicates that the data on eth_data port is valid. eth_errorOut1 eth_dataOut8Ethernet frame data that comes from Ethernet PHY module on the board. For an Ethernet link at 100Mbps only eth_data[3:0] is valid. If it is a 1Gbps link all the 8 bits are valid.

7. Ethernet Driver – Simulation Manager Interface Signal NameIn/OutWidthDescription Cmd_enIn1Active High. Sync signal for the cmd and param signals. Cmd[7:0]In8Command code from the simulation manager, explained in next slide. Param[7:0]In8Parameter word sent along with a command. Explained in next slide. src_mac_addr[47:0]In48Source MAC address dest_mac_addr[47:0]In48Destination MAC address src_ip_addr[31:0]In24Source IP address dest_ip_addr[31:0]In24Destination IP address data[0 to 1521][7:0]In(1522)(8)Ethernet data to be sent to the SDR design data_sizeIn11Size of the Ethernet data to be sent – i.e., only the data size no.of bytes of the above data port are valid for a given frame eth_frame_sentOut1Active High. Signal indicating that a frame has been sent. 7 SDR Test Bench

8. 8 Ethernet Driver – Commands CommandCommand Code ParametersDescription send_frame00000001Param[1:0] – add_hdr indicates whether the Ethernet driver has to add headers before sending out data 00 - no need of adding headers 01 - Add Ethernet header only 10, 11 - Add both Ethernet and IP headers Send ethernet frame to the SDR design.

9. SDR Test Bench 9 Monitors Monitors provided in this design are DiBo SPI Monitor WiBo Control Monitor which consists of 1. WiBo SPI Monitor 2. U2 Monitor 3. Antenna Switch Monitor - Antenna Switches are treated as a register by introducing a dummy ant_sw_sync signal which is used only for simulation purposes. Each of the above is used to monitor a set of registers (SPI registers, u2, antenna switches) and they use a common block called the register monitor. Register monitor keeps a record of register contents and register write operations with the help of text files. It can also take various commands from the simulation manager, such as comparing all the register contents with the values given in a text file, comparing a particular register value etc., and send a response back to the simulation manager. Following slides explain the register monitor first, and then discuss how each of the above monitors uses the register monitor to perform the required function.

10. SDR Test Bench 10 Register Monitor

11. SDR Test Bench 11 Register Monitor – Register read/write interface Signal NameIn/OutWidthDescription reg_reqIn1Active high, request to read or write to a register reg_rdnwrIn11 – register read request 0 – register write request reg_noInADDR_WIDTH (Generic) Address of the register to be read or written to. reg_wr_dataInDATA_WIDTH (Generic) Data to be written into the register with address reg_no reg_rd_dataOutDATA_WIDTH (Generic) Requested register data

12. SDR Test Bench 12 Register Monitor – Simulation Manager Interface Signal NameIn/OutWidthDescription CmdIn8Coded command sent by the simulation manager. Explained in next slide ParamIn32Contents of the param word are interpreted according to the command code. Explained in next silde.Currently the param word is being used as follows Param[7:0] - register number Param[31:8] – register data With command 00000001 – compare next register write, the register monitor checks if the next write is being made to the register number given in the param word and if the register write data is equal to that given in the param word. With command 00000010 – compare current register contents, the register monitor checks if the data in the register param[7:0] is same as param[31:8] Golden_file_nameInStringFile name of the new golden file. Before the simulation manager sends a compare files command(00000011), it can send an update golden file command(10000000) to change to golden file. Along with that command it sends the new golden_file_name. Cmd_passInDATA_WIDTH (Generic) Active High, indicating that the command was successfully completed. In case of compare commands it means that there isa match. Cmd_failOutDATA_WIDTH (Generic) Active High, indicates that the command has failed. Reason for the failure is given in the cmd_file_tag Cmd_fail_tagOut40001 - Bad command 0010 - Bad Param 0011 - Can’t open file 1000- Register content mismatch (file or single register)

13. SDR Test Bench 13 Register Monitor – Commands CommandCommand Code ParametersDescription chk_next_wr00000001Param[7:0] – register address Param[31:8] – register data the register monitor checks if the next write is being made to the register number given in the param word and if the register write data is equal to that given in the param word. chk_reg_con00000010Param[7:0] – register address Param[31:8] – register data compare current register contents, the register monitor checks if the data in the register param[7:0] is same as param[31:8] cmp_file00000011Not usedcompare register content file with the golden file cnt_wr00000100Param[31 :0] – number of write operations Count the number of write operations from the time the command has been sent,and send a response cmd_pass once the count is equal to that in the param word. update_file10000000Not usedUpdate the golden file. File name is given as an input string(golden_file_name)

14. SDR Test Bench 14 Register Monitor – Files Register Log File – The register monitor logs all its read/write operations in the this file. A register log file can look as follows No Rd/Wr Register No Register Data ************************************************************************************* 1 Read 0 00010010 2 Write 0 00011110 4 Write 4 01010101 Register Content File – Register monitor keeps a record of the register contents in this file. The initial contents are by default all 0s, but they can be non-zero too. Every write operation results in updating this file and for every read operation, register data is fetched from this file. It can look as follows Register No Register Data ************************************************************ 0 01101000 1 00000000 2 01010000 Error File - Read/write errors(Ex: Invalid register no, read not supported ), command failures are logged in the error file. The error file may look like this Operation Number Error ********************************************************************************* Read 3 Invalid register no : 68 sim_mgr cmd 2 Bad Command code 00011111

15. SDR Test Bench 15 SPI Monitor An SPI monitor consists of an SPI emulator and a register monitor. SPI emulator interprets the SPI input signals and performs register read/write operations. Write operation corresponds to sending an update to the register update monitor, with the register address and data information. Read operation corresponds to fetching register data from the register monitor, and sending out the data bits serially. SPI emulator architecture depends on the actual chip that is being used (Ex MAX 2829 or AD9862). Though they have a standard 3 or 4-wire SPI interface, read/write operations are performed in a different way in each of the chips.

16. SDR Test Bench 16 DiBo SPI Monitor DiBo SPI monitor emulates the SPI interface and registers of AD9862.

17. SDR Test Bench 17 Signal NameIn/OutWidthDescription senIn1Active low, used to gate read and write operations. When sen is high, sdio and sdo are three-stated. sclkIn1clk used to synchronize SPI reads/writes. (Maximum bit rate -16 MHz).A register update is sent after the 16th rising clock edge (and 24th rising clock edge for the dual byte case). Incomplete read/write operations are ignored. sdioInout1Serial bidirectional line used by default as input to write to the SPI registers. Used as an output for read operations in 3-wire mode. SDIO BiDir register( Register 0 Bit 7) is used to configure the SPI interface in 3-wire or 4-wire mode sdoOut1Default output for read operations. (4-wire mode) DiBo SPI Monitor – SDR Design Interface

18. SDR Test Bench 18 WiBo Control Monitor WiBo control monitor emulates the following - U2 – the shift register MM74HC595 - SPI interface and registers on MAX2829 - Antenna Switches U3, U4, U5

19. SDR Test Bench 19 WiBo Control Monitor

20. SDR Test Bench 20 WiBo SPI Monitor WiBo SPI emulator emulates the SPI interface and registers of MAX2829. MAX2829 SPI is a 3-wire interface which does not support read operations. It has 13 registers which are 14 bit wide as opposed to 64, 8 bit registers in AD9862. Also, MAX2829 does not support dual word write operations as AD9862. With these and other differences in operation, though the same interface is maintained (with sdo floating – three stated always) for WiBo spi monitor, its architecture is completely different.

21. SDR Test Bench 21 Signal NameIn/OutWidthDescription senIn1Active low. This signal is connected to cs(bar) of the SPI interface of MAX2829. It indicates that the clock is active. A register update is sent when wibo_sen transitions high. Only the last 18 bits shifted in are retained,and no check is made on the number of clock pulses. sclkIn1Clk used to synchronize SPI writes. (Maximum bit rate -16 MHz). Data is shifted on the rising edge. This is also connected to the shift clock (sck) of U2. sdioInout1Though this is an inout port, the wibo spi emulator uses it only as an input port for receiving serial data sdoOut1This pin is not used by the wibo spi emulator. It is always tristated. WiBo SPI Monitor – SDR Design Interface

22. SDR Test Bench 22 WiBo SPI Emulator – Register Monitor Interface Signal NameIn/OutWidthDescription reg_reqIn1Active high, request to write to a register reg_rdnwrIn11 – register read request 0 – register write request For WiBo SPI emulator, it is always 0. reg_noIn4Address of the register to be written to. reg_wr_dataIn14Data to be written into the register with address reg_no reg_rd_dataOut14Though this port exists, it is never used by the WiBo SPI emulator

23. SDR Test Bench 23 U2 Monitor

24. SDR Test Bench 24 U2 Monitor – SDR Design Interface Signal NameIn/OutWidthDescription U2_senIn1This is connected to the storage clock (rck) of U2. On a rising edge of this clock, data in the shift register is transferred to the storage register i.e., to the output linesof U2. sclkIn1Clock used for the shift register (sck). Data is shifted on the rising edge. This is a shared port between u2 and WiBo SPI (sclk) sdataIn1Serial data shifted into the register. This is a shared port between u2 and WiBo SPI(sdio)

25. SDR Test Bench 25 U2 Emulator – Register Monitor Interface Signal NameIn/OutWidthDescription reg_reqIn1Active high, request to write to U2 reg_rdnwrIn11 – register read request 0 – register write request For U2 emulator, it is always 0. reg_noIn1Since there is only 1 register, the register number is always given as 0. reg_wr_dataIn8Data to be written to U2 reg_rd_dataOut8Though this port exists, it is never used by the u2 emulator.

26. SDR Test Bench 26 Antenna Switch Monitor

27. SDR Test Bench 27 Signal NameIn/OutWidthDescription radio_syncIn1Active High. Indicates that the data on the radio_iox pins is valid. radio_io5In1This signal is used to turn on U3 – tx antenna switch. When it is on, the switch is crossed giving 2.4GHz output to A03 and 5.6 GHz output to A04. radio_io6In1This signal is used to turn on U4 – rx antenna switch. When it is on, the switch is crossed, routing antenna A02 output to 2.4GHz input of MAX2829 and A01 output to 5.6GHz input of MAX2829. radio_io7In1A spare signal that could be used to control the antenna switches. Antenna Switch Monitor – SDR Design Interface

28. SDR Test Bench 28 Antenna Switch Emulator – Register Monitor Interface Signal NameIn/OutWidthDescription reg_reqIn1Active high, request to write to the antenna switches reg_rdnwrIn1For antenna switch emulator this is always 0 reg_noIn1Since there is only 1 register, the register number is always given as 0. reg_wr_dataIn3Data to be written to the antenna switches reg_rd_dataOut8Though this port exists, it is never used by the antenna switch emulator

29. Simulation Manager SDR Test Bench 29

30. SDR Test Bench 30 Simulation manager shown in the figure, has an interface that is defined to interact with Ethernet driver, DiBo SPI monitor, and WiBo control monitor. This interface has to be modified if any more blocks like Ethernet monitor, RS232 driver etc., are added to the test bench For a given interface, the simulation manager can have different architectures. Ex: 2 designs that can be tested with this simulation manager - test_v5lx_top.vhd - ocrp_top.vhd these designs can have different architectures for the simulation manager. Simulation Manager

31. SDR Test Bench 31 Simulation Manager – Architecture for OCRP OCRP is designed such that all control is through Ethernet only i.e., SPI register writes, U2 and antenna switch updates can be done only through control commands sent over Ethernet. The simulation manager for OCRP does the following 1)takes an Ethernet command file and sends commands to the Ethernet driver. 2)After sending all the Ethernet frames, it sends a file compare command to all the monitors along with appropriate golden files. 3)Once it receives responses from the monitors, it reports them to the report file.

32. SDR Test Bench 32 Ethernet Command File Contains a list of command file names and the properties associated with these files. These properties can vary with the simulation manager (sim_mgr)architecture. For OCRP, the following file format may be followed Command Type Add Ethernet Header Add IP header File Name **************************************************************************************************** Cntrl Yes Yes wibo_freq_2_437.txt Cntrl Yes Yes set_rx.txt Data No No mod_data.txt The test bench top file (tb_top.vhd) is instantiated with its ETH_CMD_FILE generic set to the Ethernet command file name. This is then passed down to the sim_mgr. The sim_mgr reads data from each of the files in the list into an array of bytes and sends it to the ethernet driver along with a command and a param word. Report File The simulation manager logs all the commands that it sends and the responses obtained in this file. A report file may look as follows ********************************************************************************************* Ethernet driver command sent ********************************************************************************************* Check next update command sent to DiBo Monitor ********************************************************************************************* DiBo command pass Error File The simulation manager reports any errors in simulation, by writing to this file… Simulation Manager – Files for OCRP

33. SDR Test Bench 33 Simulation Manager – Architecture for test_v5lx_top.vhd Test_v5lx_top is the first SDR design, developed to test the SDR platform (v1.0). This design does not take any data commands. It takes control commands with a fixed length – Though WiBo and DiBo can be controlled through Ethernet, initial controls are sent by the design itself. Whenever the design receives a control command, it updates all the registers on both DiBo and WiBo. So, the simulation manager for test_v5lx_top does the following 1) takes an Ethernet command file and drives the Ethernet driver. The Ethernet command file looks similar to that of OCRP, except that the command type field is not used. 2) Waits for the first set of register updates before sending the first command to the Ethernet driver. 3) After sending a command to the Ethernet driver, it waits for another set of register updates before sending the next command.