1. Real-Time Kernel (Part 1)
Operating Systems Design and Implementation

2. Basic Real-Time Concepts
Soft versus Hard real-time
soft--as fast as possible but missing deadline is tolerable
hard--correct and on time

3. Foreground/Background Systems
Often referred to as super-loops
Infinite loop
calling modules
ISR
Handle
Asynchronous
Events
ISR
ISR
Interruption
occurred
Background
(task level)
Foreground
(interrupt level)

4. Interrupt Service Routines
Handle critical operations
can take longer than they should
make data available for background routines
processing of such information is referred to task-level response

5. Example: EFI System (Electronic Fuel Injection)
What are the components?
Throttle Body
Cold start solenoid
Air-flow meter
Injectors
O2 sensor
Water temperature sensor
ECU
Distributor sensors
High pressure fuel pump
manifold sensor

6. EFI System How does it work?
fundamentally, it manages three necessities to start and maintain operation of a gasoline engine
fuel
spark
air

7. EFI System What happen to the EFI system when you start a car?
What happen to the EFI system when you drive a car?

8. Dissecting EFI System
Tasks
ISRs

9. EFI System Critical section (atomic or indivisible) Mutual exclusion?
any possible critical regions in our tasks?
Mutual exclusion?
Reentrant code?
functions can be used by multiple tasks without causing data corruption
Priority inversion problem?

10. Priority Inversion Assume task 3 has lower priority than task 1.
Task 1 is doing I/O so Task 3 gets to run
Task 3 is in the middle of accessing a shared resource (obtain semaphore)
Task 1 finishes so it preempts Task 3
Task 1 wants to access the same resource but can’t since Task 3 has the semaphore

11. Priority Inversion Priority Inheritance
In this scenario, the priority of Task 1 is reduced to that of Task 3.
What is a good solution?
Priority Inheritance

12. Priority Inversion Priority Inheritance
Task 1 is doing I/O so Task 3 gets to run
Task 3 is in the middle of accessing a shared resource (obtain semaphore)
Task 1 finishes so it preempts Task 3
Task 1 wants to access the same resource but can’t since Task 3 has the semaphore; thus the kernel raises the priority of Task 3 to the same as Task 1
Task 3 gets to finish and releases the resource. The priority is reset to the original value
Task 1 is selected if it still has the highest priority

13. Assigning Task Priority
Rate monotonic scheduling
tasks with the highest rate of execution are given the highest priority
Assume all tasks are periodic
Tasks do not synchronize with another, share resources, and exchange data
Preemptive scheduling is used

14. Assigning Task Priority
Number of Tasks
n(21/n - 1) 1 2
0.82 3
0.77 4
0.75 5
0.74 … -
0.69

15. Providing Mutual Exclusion
Disabling interrupt
Test and Set operation
hardware support (TSL operation)
Disabling scheduler
Semaphores
how is semaphore implemented?

16. Disabling Interrupt
X86
CLI (disable interrupt)
STI (enable interrupt)

17. Busy Waiting

18. Busy Waiting

19. Semaphore Is a type that has a counter and a delay queue
require OS support as processes in the delay queue are blocked
implementation often requires other primitive support (disabling interrupt, etc.)

20. Semaphore assumes the existence of binary semaphore operations
upb and downb implemented with a test-and-set
instruction and busy waiting

21. Intertask Communiciation
Message mailbox
Message queues
often use to process interrupt

22. Interrupts
A hardware mechanism used to notify the CPU that asynchronous events have occurred
Upon completion, the programs return to:
background for a foreground/background system
the interrupted task for non-premptive kernel
the higest priority task ready to run for premptive kernel

23. Example: Interrupt in NIOS
IE bit to enabling interrupt
PRI bits for priority
MISC bits for interrupt control

24. Source of Exceptions (NIOS)
External Hardware interrupt Sources
External logic for producing the 6-bits interrupt number & asserting the IRQ input pin is automatically generated by the SOPC builder and is included in the Peripheral Bus Module (PBM).
Internal Exception Sources
2 sources of internal exceptions
Register window-overflow, Register window-underflow
Direct Software Exceptions
Software can request that control be transferred to an exception handler by issuing a TRAP instruction.

25. External Hardware Interrupts
Active-high interrupt signal: irq
Level sensitive
Sampled synchronously at the rising edge of Nios clock
Should stay asserted until the interrupt is acknowledged by software
6-bit Input Interrupt Number: irq_number[5:0]
Identifies the highest priority interrupt currently requested
Highest priority = 0 (irq #0 to #15 are reserved)
Lowest priority = 63

26. External Hardware Interrupts
Nios will process the indicated exception if
IE= 1 – i.e. external interrupts & internal exceptions are enabled, AND
The interrupt number is smaller (lower or equal) than the IPRI field value

27. Interrupt Service Routine Handler
nr_installuserisr( int trapNumber, void *ISRProcedure, int context)
trapNumber is the exception number to be associated with a service routine
ISRProcedure is a routine which has a prototype of typedef void (*Nios_isrhandlerproc) (int context);
context is a value that will be passed to the routine specified by isrProcedure

28. ISR Handler
This routine installs an interrupt service routine for a specific exception number
If nr_installuserisr() is used to set up the exception handler, then the exception handler can be an ordinary C routine

29. ISR Process Interrupt occurs Current state is saved (Context)
Memory
Main Program
Save
Context
Interrupt occurs
Current state is saved (Context)
ISR address is retrieved from the vector table based on the interrupt number
Jump to ISR routine
Runs to completion
Context is restored
Program resumes
Restore
Context
ISR
Vector Table

30. ISR Implementation Specify your # IRQ Declare your IRQ subroutines
Update the ISR vector table
ROM instruction
RAM
stack
@irq_subroutine 0 …
@clock_adj_ISR
@RealTime_ISR
@irq_subroutine 63
Vector Table
0xFFFF
0xFF0F
0xFF0E
0xFFC0
Write your IRQ Subroutine
Write your IRQ Subroutine