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E.Beuville, M.Belding, A.Costello, R.Hansen, S.Petronio

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Presentation on theme: "E.Beuville, M.Belding, A.Costello, R.Hansen, S.Petronio"— Presentation transcript:

1 E.Beuville, M.Belding, A.Costello, R.Hansen, S.Petronio
A High Performance, Low Noise, 128-Channel Readout Integrated Circuit for Instrumentation and X-Ray Applications E.Beuville, M.Belding, A.Costello, R.Hansen, S.Petronio

2 Indigo Systems Background (Merged with FLIR, January 2004)
Infra-Red Systems Manufacturer  Imaging and Thermography  Surveillance, Firefighting, Industrial, Military… IR sensor fabrication facility (GaAs, InSb, mBolo) Readout Integrated Circuit (ROIC) Core Capability Large 2D ROIC pixel arrays (1k x 1k at 15um pixel size) Custom IC (mixed signal)  IR applications  X-ray and mammography applications  Implantable devices  Space applications  Instrumentation

3 ISC9717 ROIC Description Design 128 Channels, Low-Noise ROIC for Flat Panel Array and Instrumentation 80um channel pitch Low noise charge amplifier (programmable gain) Low Pass Filter (programmable time constant) Correlated Double Sampling (programmable gain) On-Chip ADC (programmable 9 to 14 bits gray-code output) C.D.S. Amplifier Charge Integrator Low Pass Filter Track-and-Hold 9-14 Bit ADC Gain Gain Time Constant Time Constant Gain Gain Resolution Resolution 2 4 4 ADC ADC 9 to 14bit Integrator LPF LPF CDS CDS T/H T/H 9 to 14bit 9 to 14bit

4 Applications and Detectors Compatibility
Wide Range of Applications Wide Range of Detectors  Digital X-ray Medical Imaging - Radiography - Fluoroscopy - Mammography - Angiography - Tomography  Flat Panel X-ray Sensors (TFT) - Cesium Iodide (CsI) or other scintillators - Selenium (Se) - Amorphous Silicon - Photodiode  Instrumentation - Airport screening - Non-Destructive Testing - CT scan, PET imaging - Astrophysics applications - Nuclear Science - Industrial Instrumentation  Solid-State Detectors - Silicon Detectors (Si) - Cadmium Zinc Telluride (CdZnTe) - Gallium Arsenide (GaAs) - Germanium (Ge)

5 Application to X-ray Flat Panel
ISC9717 reading out TFT flat panel array Wire bonded or Tape Automated Bonding (TAB) Programmable readout direction TFT Array (split in 2) Gate Driver Gate Driver 14 bits ISC9717 ISC9717 14 bits 14 bits ISC9717 ISC9717 14 bits Column Select Line DATA Line + Sensor Pixel Detector Bias

6 ISC9717 Serial Command Register
Gain Control (Integrator and CDS) Full dynamic range from 48fC (3x105 e-/hole) to 12pC (75x106 e-/hole) Integration While Read mode Higher readout rate Integration Then Read mode Lower noise Integration time control Integration time adjusted by controlling the clock (24us to few ms) Readout direction (left or right) Allows the readout IC to be connected on both sides of 2D sensors Averaging mode (two adjacent channels averaged) Improved signal-to-noise ratio Higher readout rates ADC resolution (9 to 14 bit) Higher readout rate for lower ADC resolution Current mode output (reduced clock feedthrough)

7 Charge TransImpedance Amplifier (CTIA)
Folded cascode architecture Differential amplifier  large PSRR P channel input transistors  low 1/f noise Folded cascode  high gain and dynamic range Adjustment of reference  hole or electron collection VREF_IN = 1.5 to 3.5V 1.0V 2.5V range (hole coll.) 4.5V 3.0V range (e- coll.) VREF_IN=1.5V VREF_IN=3.5V 5V 6 5 VREF_IN INPUT 1 2 3 4 CF = 0.5pF, 1pF, 2pF, 4pF GND

8 Low Pass Filter (LPF) Simple first order low pass filter
Limit the bandwidth (f-3dB from 32 to 200kHz) Noise attenuation RC filter implementation RC=1us with Resistor (1Meg) and Capacitor (1pF) Resistor can be too large to implement (HiRes poly=1k/SQ)  Using transistor’s transconductance gm Time constant = CLPF/gm Programmable time constant 0.8us, 1.3us, 2.8us, 3.3us 1us, 2us, 4us, 5us with external voltage adjustment

9 Low Pass Filter (Slew / Rise Time Constraint)
Slew rate and settling Measurement time for 14bit settling increases for large signal amplitude due to slew rate Slew rate: Settling: VP settling SR Approximation: t1 t2 t3 TM t

10 Low Pass Filter Implementation
RC+SR t = CLPF/gm Cf out VIN gm LPF VLPF VGS CLPF RST SPICE sim. At t=0, VGS is large  large current  large SR  large gm  small t When VLPF reaches VIN  small current (settles with t) 10us Tsettle RC+SR 8us LPF 6us  non-linear settling  linear (no bulk effect)  adjustable time constant 10bit settling 4us 0.01 0.1 1 Log(VIN) 10

11 Correlated Double Sampling Amplifier (CDS)
Remove offset and CTIA kTC noise After integrator reset released  store and subtract kTCINTEG Reduces 1/f noise (increases thermal noise) Programmable gain X1, x2, x4, x8, x32 CLAMP2 V2/Hz C2 CDS_BIT[0-3] VREF_CDS CLAMP1 TRACK C1 + Gain =C1/C2 VREF_CDS f(Hz)

12 Analog-to-Digital Converter
One ADC per channel Single slope ADC On-chip voltage ramp generator (programmable) Grey code counter  1 bit changing at a time VREF_ADC RST RST RST_ADC VREF_ADC ramp Signal (held) INPUT Cc Input Latches 14 RAMP_IN 14 t 9-14bit Gray Code Counter Gray Code Counter Latch

13 ADC Ramp Generator Charge pump architecture
Programmable ramp for 9 to 14 bit conversion VPOS Clock = 40ns (twice Master clock) VLSB = VADJ_RAMP C1 C2+CL C2 RST_ADC RAMP_OUT CL VADJ_RAMP 40ns VLSB C1 C1 f f Slope controlled by VADJ_RAMP and the C1/(C2+CL) ratio  Adjustment of the LSB level from 9bit to 14bit Non-overlapping clock f f GND

14 Low Impedance  DV < 50mV
Current Mode Output Current mode output (0.5mA)  high speed output  low voltage output  low power  reduced clock feedthrough CLOCK SYNC Data Out BIT9 BIT8 BIT7 ROIC Current Mode Receiver Low Impedance  DV < 50mV VPD 10k . 0.5mA PN3640 CL<30pF 1V 700 Data rate = 12.5MHz Suggested current mode receiver

15 ISC9717 Noise Analysis and Measurements
All noise sources taken into account BWAmp VkTC CLAMP VkTCcds T/H CT/H + SELECT CF RST vAmp v1/f CINT INT LPF CC1 CC2 Vout vLine VkTCf Detector Noise +Quantization Noise For detector current integration

16 Noise Acquisition External input capacitor added on few channels
60Hz noise pick up from the inputs / test board  Removed by subtracting 2 channels (increases the noise by √2) No input cap 10pF 100pF 50pF 60Hz time 128 channel

17 Noise Measurement Equivalent Noise Charge (ENC) referred to the input
500 1000 1500 2000 2500 3000 3500 CDET 20pF 40pF 60pF 80pF 100pF ENC (e-RMS)  Analysis High resolution setting: Cf = 1pF tLPF=1us GainCDS = 32 ADC = 14bit

18 Noise as a Function of LPF
Dominant thermal noise (V2RMS)  1/tLPF tLPF 1us 2us 3us 4us 5us 1000 1200 1400 1600 1800 2000 ENC (e-RMS)  Analysis  Measurement CDET= 50pF Cf = 0.5pF GainCDS = 8 ADC = 14bit  ENC  1600e-RMS  Optimum noise for 5us LPF time constant

19 ISC9717 Averaging Mode Averaging mode SNR improvement
Increase readout rate by a factor 2 T/H VAVG = (V1 + V2) / 2 To ADC V1 (V1 + V2) 2√ (V2n1 + V2n2) Odd channel SNR = CHOLD AVG  √2 SNR improvement T/H Even channel V2 CHOLD

20 ISC9717 Performance Summary
Specifications Nominal Comments Number of channel 128 channel/chip 80um Input bonding pad pitch Clock frequency  12.5MHz Low voltage differential clock Integrator gain control CF=0.5pF, 1pF, 2pF, 4pF 2BIT gain control Charge collection Electrons (≤ 75x106 e-) Hole (≤ 62x106 hole) VREF_INTEG = 1.5V for e- collection VREF_INTEG = 3.0V for hole collection Low-Pass-Filter time constant 0.8us, 1.3us, 2.8us, 3.3us (1us, 2us, 4us, 5us) 2BIT (2 capacitors selectable) 10% tolerance With external voltage adjustment Correlated Double Sampling Gain = x1, x2, x4, x8, x32 Removes the ROIC kTC and 1/f noise Crosstalk   0.25% (internal to ROIC) Total power dissipation  220mW 200mW nominal ADC resolution 9 to 14 bits (gray code output) Programmable ADC resolution (ADC frequency=25MHz) Current mode output 9 to14 output used Parallel output (single ended 0.5mA 20%) ENC (GINTEG =2mV/fC, GCDS=32, ADC=9bit)  1200 e-RMS referred to input Measured noise with 50pF input capacitor Noise depends on systems noise performance GCDS=8, ADC=14bit)  1400 e-RMS referred to input GCDS=1, ADC=14bit)  2300 e-RMS referred to input

21 Standard ASIC Product Package
ISC9717 ROIC USER MANUAL DOC # VERSION 2.3 October 14, 2003 Copyright Indigo Systems Corporation 2003 Information furnished by Indigo Systems Corporation is believed to be accurate. However, no responsibility is assumed by Indigo Systems Corporation for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Indigo Systems Corporation. Standard ASICs By the die in fully tested wafer form 487 die / wafer AMI 0.5um process Typical yield is above 90% Each wafer:  complete test data on CD-ROM CD-ROM contains PRISM test data explorer software Physical database in GDSII format provided on CD-ROM Complete set of documentation Design and Users Guide Technical Application Notes Physical Interface Drawings Applications engineering support  successful integration of sensor with ROIC

22 Integration While Read
Simultaneous integration, A/D conversion and readout  Higher frame rate 28.6kHz conversion rate at 9 bit resolution (Clock = 12.5MHz) 1.49kHz conversion rate at 14 bit resolution Stop CLK for longer integration time tINTEG=11.68us + 2(N-1)/fCLK

23 Integration Then Read Integration, ADC and readout performed sequentially  Lower Noise 15.1kHz conversion rate at 9 bit ADC resolution (Clock = 12.5MHz) 1.42kHz conversion rate at 14 bit ADC resolution Stop CLK for longer integration time tINTEG=34.4us

24 Noise Measurement (1 of 2)
Equivalent Noise Charge (ENC) referred to the input CDET 500 1000 1500 2000 2500 3000 3500 20pF 40pF 60pF 80pF 100pF ENC (e-RMS)  Analysis  Measurement High gain setting: Cf = 0.5pF tLPF=1us GainCDS = 32 ADC = 9bit CBOARD  4.0pF


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