2. Programmable Logic Takes Market Share from Others
Total 1996 Market – $9.5B
Total 2001 Market – $15.8B
Mask Programmed Gate Arrays $7.4B
Mask Programmed Gate Arrays $5.6B
47%
59%
21%
20%
16%
37%
Standard Logic $2.0B
Programmable Logic Share
$1.9B
Standard Logic $2.6B
Programmable
Logic Share $5.8B
Source: Dataquest, May 1997

3. CMOS Programmable Logic Market
Total CMOS
Programmable Logic
EPLD
FPGA
1996
$959
2001
$2400
1996
$884
2001
$2687
SPLD
CPLD
1996
$411
2001
$279
1996
$548
2001
$2121
CAGR 33%
Source: In-Stat May 1997

4. ASIC Alternatives Xilinx Product Line Custom Highest Density
ASIC Tools
Gate
Array
Xilinx
Product
Line
Custom
Transparent
Conversion
100% Tested
HardWire(TM)
Array
Programmable
GA Architecture
High Density
ASIC Tools
FPGA
Programmable
PAL Architecture
Medium Density
PAL-like Tools
EPLD
Programmable
AND/OR
Architecture
Low Density
Simple Tools
PAL™

5. Company Milestones 1984 Xilinx Founded
1985 Introduced first field programmable gate array (FPGA)
1987 Introduced second family of FPGAs
1988 Established subsidiary in Japan
1989 More than one million devices sold
1990 Initial public offering
1991 Introduced third family of FPGAs
1992 Expanded into complex programmable logic (CPLDs)
1993 Established Xilinx Hong Kong
1995 Xilinx ranked 10th largest ASIC supplier; Xilinx Ireland opens
1996 Xilinx ranked 8th largest ASIC supplier
1997 Industry’s first advanced 0.35 & 0.25 micron FPGAs
1998 Introduced low-cost Spartan FPGAs with RAM & cores

6. Why Xilinx? Silicon Software Service Process Technology
Largest, fastest, lowest power FPGAs
Lowest cost CPLDs
Software
Alliance Series: HDL, synthesis, EDA integration, optimization
Foundation Series: ready to use, complete solutions
LogiCORES & AllianceCORES: optimized and supported
Service
Most comprehensive field and on-line technical support
Advanced Internet Web solutions
Process Technology
Deep submicron capacity — Sampling 0.25 micron now
Better price, performance, density

7. Xilinx Revenue Growth 1990–1998 Fiscal Year Revenues $ Millions $614
$568
$561
$355
$256
$178
$136
$98
$50
Fiscal year ends March 31

8. High Density FPGA Sales ( gates, Previous 4 Quarters)
13K
100 80 60
Revenue (M$) 40 20
Xilinx
Xilinx
Lucent
Lucent
Altera
Altera
Xilinx sells more high-density FPGAs than the rest of industry combined.
This is a result of Xilinx’ past and present leadership.

9. Worldwide Sales Japan Rest of World Europe 10% 5% 22% 63%
North America
Source: Xilinx

10. Military, High Reliability
Who’s Using Xilinx
Industrial &
Instrumentation
Networking
Military, High Reliability
12%
16% 4%
1% Misc
32%
35%
Data Processing
Communications
Source: Xilinx

11. Where Xilinx Fits in the Electronics Industry
Key components of an electronics system
Processor
Memory
Logic
Xilinx is the Leading Innovator
of Complete
Programmable Logic Solutions

12. How Customers Use Programmable Logic
Xilinx Provides Standard Parts “Blank” Integrated Circuits
Customers Create Custom Circuits with Xilinx Software Tools
When Design Is Final, Customers Go into Immediate Production

13. Market Segments Communications Computers Instruments Medical equipment
Networks
Consumer electronics

14. Xilinx Application Examples
Broadcast Communications
HDTV
CATV (Scramblers & Decoders)
Satellite Links
Studio Equipment
Video Disk Recorder
Consumer
Digital Audio Decoder
Arcade Games
Video Games
Karaoke Systems
Transportation
Railway Systems
Auto Digital Audio Systems
Industrial
Test And Measurement Equipment
Medical Equipment
Motor/Motion Control
Semi. Processing Equipment
PC Projection Units
Robotics
ASIC Emulators
Postage Systems
Vision Systems
µP Emulators
Lottery Systems
Military
Computer And Communications Systems
Missile Guidance Avionics
Fire Control
Computer
Memory Interfaces
DMA Controllers
Local And Mezzanine Bus Interfaces
Cache Controllers
SSP Co-Processors
Multi-Media
Graphics
Peripherals
Disk Controllers
Video Controllers
FAX (Incl. PCMCIA)
Barcode Readers
Teller Machines
Tape Controllers
Sound Cards
Modems (Incl. PCMCIA)
POS Systems
Data Acquisition Cards
Terminals
Printers
Scanners
Copiers
Data Communications
Multiplexers
Routers
Video Conferencing
Encryption/Decryption
Switches
Bridges
Modems (incl. PCMCIA)
Data Compression
LAN Hubs
FDDI
Wireless LANS (Incl. PCMCIA)
Telecommunications
Central Office Switches
SONET Interfaces
Cellular Base Stations
Auto. Directory Assistance
Fiber Optic Interfaces
ATM
ISDN Interfaces
Voic Controllers
PBX Equipment
T1 Multiplexers
Speech Synthesis
Pay Phone Control

15. Strategic Business Model Ensures Focus
“Fabless” strategy
Leading edge IC process technology
Wafer capacity at competitive prices
Fastest, lowest cost, densest parts
Independent sales organization
Sales is a variable cost
Permits greater reach—over 15,000 customers
Focus on key strengths
Research and development
Marketing
Applications engineering 1

16. Xilinx’ Fabless Advantage
$136M equity investment in UMC
guaranteed 33% capacity of new 8” fab
$300M advanced payment to Seiko
guaranteed capacity for next 5 years
Access to 0.25 & 0.18 leading edge fab in 1997
Guaranteed fab access to support $2B/year revenue
50 engineers working in-house on process technology
Developed FastFLASH process
Developed Micro-Via antifuse process

17. Process Technology Leadership Roadmap
Feature Size (µm)
5V “cost reduction line” has
been valid for >10 years
5.0 V
3.3 V
2.5 V
1.8 V
Year

18. Density Roadmap 2001 -> 150,000 logic cells (2.0M gates)
1,000,000
12M
1.2M
120K
12K
2.0M gates
100,000
Density (logic cells)
Gates
10,000
Year
1,000
1994
1996
1998
2000
2002
Year
2001 -> 150,000 logic cells (2.0M gates)
logic cell = 4-input LUT + FF

19. Xilinx vs Other FPGA Interconnect Technology
Xilinx Interconnect
Other FPGA Interconnect
Across Chip
Across Chip
Logic
Block 1
Logic
Block 2
...
...
Logic
Block 3
Logic
Block n
Logic
Block 1
Logic
Block 2
Logic
Block n 1x 1x 4x 4x 3x 4x 1x 6x
Logic
Block
(next row)
Logic
Block
(next row)
“Segmented” Interconnect Lines
Variable Length Interconnect Lines
1 Segmented line required to connect logic cells
Smaller Die Size => Lower Cost
“Non-Segmented” Interconnect Lines
Fixed Length Interconnect Lines
3 Single Signal lines required to connect logic cells
Larger Die Size => Higher Cost
Segmented Interconnect Structure Provides Faster Logic Cell Connections

20. 1/(Tsetup+Tclock-to-out)
Performance Roadmap
200
180
160
140
120
100
System Clock Rate
1/(Tsetup+Tclock-to-out)
MHz 80 60 40 20
1995
1996
1997
1998
1999
2000
Year
Process Technology Makes this Possible
5x Improvement in 5 years

21. Power Roadmap (for constant gates & frequency)
Power  CV2f
Low power = high performance
Low power = higher reliability
non-segmented
interconnect
(others) 3x
Power
>>3x
segmented
interconnect
(Xilinx)
1996
2001
Year

22. Hardwire for High Volume 2001
Same curves, change numbers
Largest savings on biggest devices
Design Once
Risk-free migration
No test vectors $
FPGA
HardWire
Logic Cells
20k
40k
60k
80k
100k
250k
500k
750k 1M
1.25M
Gates

23. Xilinx Pioneers FPGA Packages
PQFPs &
VQFPs
BGA
3000
1000
Flip-chip
Package Pins
SBGA
100
1992
1994
1996
1998
2000
2002
Year
First to use PQFP & VQFP
First to use BGA & SBGA (Super BGA)
Investigating flip-chip today for higher integration

24. Availability of LogiCores
Buses PCI slave 33MHz PCI 3.3v slave PCI slave 66MHz PCI master 33MHz PCI 3.3v master PCI master 66MHz USB device controller ISABus Plug & Play
Telecom ATM cell delineation E1/E2/E3 framer SONET standard cores ATM Utopia master E1/E2/E3 processor OC standard cores ATM Utopia slave E1 crossconnect Echo canceller ISDN, HDLC controller E1 Add/drop mux ADSL M16450 UART SONET/SDH pointer Ethernet STS-3 parallel framer QAM/FEC
DSP FIR filters Convolution filters Math toolkit Correlators (8-128 bits) Channel models Voice models Multipliers, high speed MPEG RZ1000 DFT MAC
Basic Blocks 8237 DMA controller ASIC libraries interval controller peripheral interface CRC
Xilinx is the leader in LogiCores today

25. Xilinx FPGA Architectures
1997
11,000 Logic Cells (125k gates)
fastest RAM
5 volt tolerant IOs
buffered quad line
VersaRing IOs
6ns pin-to-pin
efficient segmented routing
lowest power
1998
32,000 Logic Cells (400k gates)
programmable IOs
Advanced Clocking
100MHz system speed
fast re-configure
hierarchical memory solution
1999
65,000 Logic Cells (800k gates)
built-in logic analyzer
D/A & A/D support
custom cores
high speed differential interface (500MHz)

26. Xilinx Leads - Others Follow
Lucent
Altera
FPGA Solution
1985
1990
1994
Pin Compatibility
1988
1990
1996
Hardwire
1990 ? ?
On-chip RAM
1991
1993
1996
FPGAs >= 20k gates
1994
1995
1996
Synopsys 5 Year
Relationship
1994 ?
1996
FPGA Cores
1995 ? ?
Shipped 40,000,000th
FPGA
1996 ? ?
Xilinx has a long history of leadership.
This trend will continue!!

27. A History of Software Innovation
Xilinx
Lucent
Altera
1985
XACT TM
Industry’s First FPGA Design Tools
1990
1986
1985
PAR TM
Industry’s First Timing-Driven Tools
1992
1993
1992
Timing WizardTM No
Answer
FPGA Specific-Timing Analysis
1994
1992
EPICTM No
Answer
Graphical Editor for Programmable ICs
1994
1992
XBLOX TM ,
LogiBLOX No
Answer
Automatic Module Generation
1994
1992
FPGA ArchitectTM
Software Architectural Modeling
1994
1995
1990
Xilinx AllianceTM No
Answer
Commitment To Open Systems
1994
1992
HLDLTM
Synopsys Constraint Interpretation
1994
Q4’96 No
Answer No
Answer
Synopsys Technology Partnership
1994
1990
Hardware DebuggerTM No
Answer No
Answer
Graphical Hardware Debugging No
Answer No
Answer
Software Internationalization
1996
1996
LogiCoresTM No
Answer No
Answer
Fully Verified and Optimized IP Cores

28. Overview the FPGA Basic Architecture

29. PLD Advantages Vs Gate Array
Faster Time to Market
Immediate Prototypes
Faster Debug
Lower Risk PCB Development
Faster Access to Hardware for Firmware/Software Development
Test Marketing Capability
Field Upgrade Potential
Solve Gate Array Obsolescence Problems 5

30. CPLDs and FPGAs CPLD FPGA Architecture PAL-like Gate array-like
Complex Programmable Logic Device Field-Programmable Gate Array
Architecture PAL-like Gate array-like
Density Low-to-medium Medium-to-high
Basic Cell Product Term CLB & LUT
Application Combination based Register Based
Performance Predictable timing Application dependent
Design Entry Equation & Schematic Schematic & HDL

31. What is the FPGA - Look up table base architecture
Programmable
Interconnect
I/O Blocks (IOBs)
Configurable
Logic Blocks (CLBs)
- Look up table base architecture
- Rich Flip Flop application design
- No predictable pin to pin delay just CLB delay
- One hot decoding & Reconfiguration
- Lower price per gate & High density and Speed

32. I/O Block (IOB) Identical I/O Blocks line the periphery of die
Input, output, or bi-directional
Registered, latched, or combinatorial
Three-state output
Programmable output slew rate

33. IOB Primitives
User explicitly defines what resources in the IOB are to be used
Special IOB primitives
Inverters may also be pulled into IOBs
Properties attached to primitives
IPAD
IBUF
Input IOB
OPAD
OBUF
Output IOB

34. Use Pull-ups/Pull-downs to Prevent Floating
Pull-up automatically connected on unused IOBs
Outputs of unused IOBs are automatically disabled
A PULLUP or PULLDOWN primitive can be specified on used IOBs
Must be instantiated in HDL
Inputs should not be left floating
Add a pull-up to design inputs that may be left floating to reduce power and noise

35. Slew Rate Control Slew rate controls output speed
Default slow slew rate reduces noise
Use fast slew rate wherever speed is important
FAST parameter on output logic primitive
OPAD
OBUF
FAST

36. Use I/O Registers Guaranteed clock to out and clock to setup
See Data Book (Pin-to-Pin Input Parameter Guidelines)
Provides fastest SYSTEM speed
Note: Will not be reported by the static timing analysis tool. . D CE Q
I/O pad
From: FPGA
Into: FPGA

37. CLB (Configurable Logic Block)
2 4-input LUTs and 1 3-input LUT
” muxes feed F/G LUTs or independent inputs to H LUT
2 edge-triggered FFs
DIN EC SR
4 outputs
Fed by “B” muxes

38. Flip-Flops in the CLB 2 Edge-triggered flip-flop per CLB
Independent Clock polarity
Selectable clock enable
Asynchronous set or reset
Local and/or global control

39. Combination Logic Resources
Lookup tables
Can be combined into multiple levels
Special cascade chain in XC5000
Carry logic
XC4000E/X/XC5000
Wide decoders
XC4000E/X
Three-state buffers

40. FPGA Lookup Tables
Two four-input functions and one three-input function
One five-input function
One four-input function and some six-input functions
Some nine-input functions
C1-C4
DIN S/R H1 F
F1-F4 H
to flip-flops &
CLB outputs G
G1-G4

41. Look-Up Tables
Combinatorial Logic is stored in Look-up Tables (LUTs) in a CLB
Example:
A B C D Z
Combinatorial Logic A B C D Z
Capacity is limited by number of inputs, not complexity
Delay through CLB is constant

42. XC4000 Select-RAM AdvantagesTM
Select the Function
- Can be Single or Dual Port
- Synchronous or Asynchronous
- “Mix and match”
Select the Size
- No wasted resources
- Scalable to needed size
Select the Location
- Can be located anywhere on die
- Adjacent to critical circuits for speed
Select the Programming Method
- Via bitstream on start-up
- During design operation
Simple to use
Address
Data WE
XC4000E
RAM
Clock
Data 2
Address 2
Optional
Dual Port

43. ROM is Equivalent to Logic
When using ROM, it is simply defining logic functions in a look-up table format
Memory might be an easier way to define logic
FPGA lookup tables are essentially blocks of RAM
Data is written during configuration
Data is read after configuration
Effectively operate as a ROM
O = I1*I2 I1 I2 O F1 F2 X
DATA(0)=0
DATA(1)=0
DATA(2)=0
DATA(3)=1 A0 A1
DOUT
As Gates
As ROM

44. RAM Provide 16X Flip-Flops
32 bits vs. 2 bits of storage
Non-simultaneous access
32x8 shift register with RAM = 11 CLBs
Using flip-flops, takes 128 CLBs for data alone
CLB
CLB D1
32 bits
2 bits D1 D Q Q1 A0 A1 O1 A2 D2 D Q Q2 A3 A4
CLK WE

45. RAM for Status registers
Provides up to a 16 to 1 density increase!
Easier routing for FPGA
Ten 16 bit read/write status registers on a bus use: 160 registers -or- 80 CLBs
In RAM the same ten status registers use:
16 four input look-up-tables -or- 8 CLBs
Vs.
Reg.
RAM

46. 16x32 FIFO Uses Only 32 CLBs with RAM
If implemented in registers:
256 CLBs for storage alone
Implemented in XC4000/SPARTAN RAM:
Storage requires only one CLB per 32 bits
Other CLBs used for addressing and control
Runs at 66 MHz in XC4000XL-2

47. Dual-Port RAM One common synchronous write port
Two asynchronous read ports
16x1 max per CLB

48. Fast Memory: Dual-Port RAM
Mhz 70
XC4000E Select-RAM 65 60
Altera’s Bottleneck = One Port 55
Data In 50
Over 2x Faster
System Performance
01001 1 45 1 1
01001 40
Data
Out
Block RAM 35
Emulated
Dual Port 30
FLEX EAB 25
FLEX Block RAM is Single-Port only. Must emulate Dual-Port cutting performance in half. 20
8 Bit
16 Bit
32 Bit
Data Bus Size
Xilinx Select-RAM delivers 2x performance for large Dual-Port RAM
Average pin to pin performance of dual port RAM with various depth from 8 to 1024 words

49. Higher Utilization: Dual-Port RAM
FLEX 10K
XC4000E/EX
Dual-Port
Emulation Logic LC
EAB LC
16x4 Dual- Port RAM
16x4 Dual Port RAM
30 Logic Cells PLUS 1 EAB
10 Logic Cells
FLEX 10K emulation logic for small Dual-Port RAM consumes more logic cells than complete Xilinx solution

50. Programmable Interconnect
Resources to create arbitrary interconnection networks
Various types of interconnect
Flexible general-purpose interconnect
Low-skew long lines
Internal three-state buffers for buses and wide functions
CLB
CLB
Switch
Matrix
CLB
CLB

51. Interconnect Hierarchy

52. Global Clock Buffers Clock Buffers are low-skew, high drive buffers
Also known as Global Buffers
Drive low-skew, high-speed long line resources
Drive all Flip-Flops and Latches in FPGA
Can also be used for high-fanout signals
Eight global buffers per FPGA
Additional clocks and high fanout signals can be routed on long lines
Otherwise routed on general interconnect
Slower and higher skew

53. Use Global Clock Buffers
Use clock buffers for highest fanout clocks
Drive low-skew, high-speed long line resources
Use BUFG primitive to be family-independent
Limit number of clocks to ease placement issues
XC4000E: 8
XC4000X : 20
XC5000: 4
Additional clocks might be routable on long lines
Otherwise routed on general interconnect
Slower and higher skew D
IPAD
BUFGS

54. Use Extra Global Buffers
Do you have high fan-out Clock Enables, or IOB Tri-states?
Drive them through a unused BUFG to lower skew and higher performance
BUFGs have less than 1ns Skew to clock and CE inputs
Have to instantiate in HDL for non-clock signals
CE or OE
INPUT P D Q CE
BUFG
CLOCK R

55. Global Buffers Interconnect
Flexibility on BUFGS allows any four of the eight to be available in any column
All connect to clock pins, but only some connect to some of the other pins

56. How to use to Xilinx Foundation Tool

57. Integration of All Tools
Hierarchy Browser allows for direct access to these files
Message Window provides error and status messages
Toolbar
Project Flowchart provides automated data transfer

58. Library Manager
The command File>Project Libraries enables the user to associate other project libraries
To open the Library Manager, click on its icon
The Library Manager organizes all macros into libraries and enables the user to delete, copy, and rename macros

59. Some Useful Commands
Use the command File>Copy Project to copy an entire Foundation project directory
Use the command File>Project Type to change the design family in one step

60. Adding Symbols To start the Schematic Editor, click on its icon
Select-and-Drag mode enables moving symbols, wires, and busses throughout the work area
To add symbols to the schematic click on the Symbol Toolbox icon
Scroll through the list to find a particular symbol, or enter it’s name at the bottom of the SC Symbols box
Replicate symbols by clicking on the symbol while the Symbols Toolbox is still active

61. Wires and Buses
To draw wires, click on the Draw Wires icon and click on the two endpoints
To draw buses, click on the Draw Buses icon and click on the two endpoints
To name a bus, double click on the bus and enter the bus name and width
To name a wire, double click on the wire and enter the node name

62. Drawing Bus Taps
Extend the bus vertically so there will be sufficient room
Terminate the bus by double-clicking the right mouse button
Name the bus
Click on the bus taps icon
Click on the bus name (in green)
Place the taps by clicking on each of the destinations starting with the least significant bit
Every bus tap will be labeled automatically

63. Query/Find Window
Query lets the user scan through the schematic to determine connections
Select a symbol or wire in the schematic, and click on the Query Mode icon
This is useful when connecting or disconnecting symbols
The Find function helps the user locate signals, chips, and pins
Find is useful when looking for objects reported by the Alliance M1 Software
Name important nets so they are easy to find later

64. Adding Hierarchy
Tie the project together with a top-level schematic that includes macros from all the Foundation Design Entry Tools
As each element of the project is created, make a symbol to represent the macro so that it can be added to the top-level schematic
Before a symbol can be created to represent a schematic macro, the macro must contain I/O Terminals that represent ports on the symbol
To enter an I/O Terminal, click on its icon, enter the terminal name, select the type of port, place it, and wire it up.

65. Entering a Level of Hierarchy
To enter a lower level of hierarchy, click on the Hierarchy Push/Pop icon and double click on the symbol
To go back to a higher level of hierarchy, double-click on a blank area of the sheet.
To create a symbol for a schematic with I/O terminals, use the command: Hierarchy>Create Macro Symbol From Current Sheet
This will place a symbol in the project library so it can be added to the top-level schematic

66. Symbol Properties
Attributes and parameters communicate necessary information to the Alliance M1 Software
Attributes and parameters are maintained in the Symbol Properties dialog box
Double-click on a symbol to enter the Symbol Properties dialog box
To make a pin assignment, double-click on the OPAD symbol, enter “LOC” in the name box and enter P49 in the description box

67. Symbol Editor
To edit a symbol, click on the Symbol Editor button inside the Symbol Properties dialog box
The Symbol Editor can be used to move ports around on a symbol so the schematic looks good

68. Importing Viewlogic Schematics
Viewlogic schematics can be imported into the Foundation schematic editor by using the command File>Import Viewlogic Schematic from the Schematic Editor
Some properties of the schematic can be modified
Importing a Viewlogic Schematic can maintain hierarchy and many of the schematics characteristics

69. Some Useful Commands
Add VCC and GND symbols by using the SC Symbols box
Sheet size can be changed by using the menu command File>Page Setup
To modify the grid, text, and colors use the menu command View>Preferences
Edit the Table printed at the bottom of every schematic page by using the menu command File>Table Setup
Zoom in, out, area, and to page by using their icons

70. LogiBLOX
LogiBLOX is a graphical interactive tool for creating high-level modules
LogiBLOX customizes components
The GUI disables selections that are incompatible with your design selections
LogiBLOX components are entered just like a macro
Functional simulation is possible without implementation
XC4000E/XL/XL support

71. Module Types Clock Dividers Comparators Data Registers Inputs/Outputs
Memories
Shift Registers
Simple Gates
Tristate Buffers
Adders
Subtracters
Counters
Constants
Pads
Multiplexers
Decoders

72. Counters
Choosing a style will determine the resources used for the module
For example, choosing the Maximum Speed option tells the software to use the Carry Logic resources if an XC4000EX FPGA has been selected
The Counters module can be binary, Johnson, LFSR, or One-Hot encoded

73. Adder/Subtracters
All arithmetic functions can utilize the Carry Logic resources
Adders/Subtracters, Accumulators, and the Comparators modules can be customized for signed/unsigned binary

74. Memories
The Memories module is useful for creating custom sized RAM, ROM, or dual-port RAM
This module will create the input decoder and output multiplexer when necessary
Specify the necessary bus width and memory depth to customize the size
Enter a memory filename to initialize a memory (for example, tenths.mem)

75. Multiplexers The Multiplexer module can have up to eight input buses
This module can be optimized for area and speed
The Mux module can utilize the tristate buffers by selecting the Wired-AND Style

76. Tri-state Buffers
This module synthesizes internal non-inverting tri-state buffers
The output enable is active-low
If an inversion is necessary add an inverter to the output enable
One or two pull-up resistors can be used to get faster transition times

77. Inputs/Outputs
The Inputs/Outputs module represents the I/O block associated with each pin on a device
Using this module allows customizable bus widths and the use of the IOB register
Buffers can be bi-directional, latched, or registered

78. Pads The Pads module represents the actual pins of a device
Location constraints can be entered for each element of a bus
The slew rate is set low by default to minimize power transients
The Delay attribute can provide 0ns hold time at the IOB register
The Pull-up/down attribute is used to prevent floating

79. Waveform Viewer
To open the Simulator, click on the Functional Simulator or the Timing Simulator icons
An implementation within the Alliance M1 software must be completed before a Timing Simulation can be completed
Contains a list of input and output nodes and an area for viewing the signals generated by the simulator
The simulator is controlled by the Simulator Toolbox

80. Inserting Probes
Add probes in the schematic to automatically load a node into the Waveform Viewer
Click on the Probes icon and click on each node name in the schematic
The probes change color in the schematic to reflect their state

81. Component Selector
Alternatively, open the Waveform Viewer, and enter nodes by using the Component Selector
Open the Component Selector by clicking on its icon in the Waveform Viewer

82. Stimulator Selector
Bc and NBc represent the normal and inverted outputs of a 16-bit counter
The square LEDs represent 16 user-defined formulas
The buttons labeled C1 - C4 represent user-defined clocks
The CS button is used with the graphical waveform editor to create a custom signal
To modify the clock frequency of the 16-bit counter, use the command Options>Preferences

83. Simulator Toolbox
Once the necessary signals have been inserted, the Step and Long buttons can be used to control the amount of time to simulate
The Forward and Reverse buttons are used to scan the waveforms for a particular event
The Power on Reset button moves the selector to the beginning of the simulation

84. Displaying Buses
To group signals, click on the MSB, hold the shift key, and click on the LSB. Then use the menu command Signal>Bus>Combine
To ungroup a bus, select the bus and use the menu command Signal>Bus>Flatten
To change the bus format, select the bus then use the menu command Signal>Bus>Display…
Any signals can be grouped within a bus

85. Some Useful Commands
To save simulation vectors, use the menu command File>Save Simulation State
To clear the waveform area, move the blue line to the beginning of the area to be deleted and use the menu command Waveform>Delete>All Waveforms after Cursor
To clear all waveforms in the viewer, click on the Delete Waveforms icon
To load a Viewlogic command file, use the command File>Run Script File