1. Verilog HDL Quick Reference Guide
Author: Nikola Jevtović Computer Science Department School of Electrical Engineering University of Belgrade
Verilog HDL Quick Reference Guide

2. Reference On-line Verilog HDL Quick Reference Guide
by Stuart Sutherland
of Sutherland HDL, Inc. - Portland, Oregon, USA
Verilog HDL Quick Reference Guide

3. Verilog HDL Quick Reference Guide
1. Hierarchy Scopes
2. Concurrency
3. Reserved Keywords
4. Lexical Conventions
5. Module Definitions
6. Module Port Declarations
7. Data Type Declarations
8. Module Instances
9. Primitive Instances
10. Procedural Blocks
11. Operators
12. Continuous Assignments
13. Task Definitions
14. Function Definitions
15. Specify Blocks
16. User Defined Primitives
Verilog HDL Quick Reference Guide
Verilog HDL Quick Reference Guide

4. Verilog HDL Quick Reference Guide
1. Hierarchy Scopes
Verilog HDL constructs that represent hierarchy scope are:
Module definitions
Function definitions
Task definitions
Named statement blocks ( begin - end or fork - join)
Specify blocks
Each scope has its own name space. An identifier name defined within a scope is unique to that scope. References to an identifier name will search first in the local scope, and then search upward through the scope hierarchy up to a module boundary.
Verilog HDL Quick Reference Guide

5. Verilog HDL Quick Reference Guide
2. Concurrency
The following Verilog HDL constructs are independent processes that are evaluated concurrently in simulation time:
Module instances
Primitive instances
Continuous assignments
Procedural blocks
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6. Verilog HDL Quick Reference Guide
3. Reserved Keywords
always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1 if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1 or
output
parameter
pmos posedge primitive pull0 pull1 pulldown pullup rcmos real realtime
reg release repeat rnmos rpmos rtran rtranif0 rtranif1
scalared signed small specify specparam strength strong0 strong1 supply0 supply1
table task time tran
tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned vectored
wait wand weak0 weak1 while wire wor xnor xor
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7. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.1 White Space Characters
blanks, tabs, newlines (carriage return), formfeeds and EOF (end-of-file).
4.2 Comments
// begins a single line comment, terminated by a newline.
/* begins a multi-line comment, terminated by a */.
4.3 Case Sensitivity
Verilog is case sensitive!
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8. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.4 Identifiers (names)
Must begin with alphabetic or underscore characters
a – z A – Z _
May contain the characters
a – z A – Z 0 – 9 _ and $
May use any character by escaping with a backslash ( \ ) at the beginning of the identifier, and terminating with a white space.
Examples
Notes
adder
legal identifier name
XOR
uppercase identifier is unique from xor keyword
\reset*
an escaped identifier (must be followed by a white space)
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9. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.5 Logic Values
The Verilog HDL has 4 logic values:
Logic Value
Description
zero, low, or false 1
one, high, or true
z or Z
high impedance (tri-stated or floating)
x or X
unknown or uninitialized
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10. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.6 Logic Strengths
The Verilog HDL has 8 logic strengths:
4 driving, 3 capacitive, and high impedance (no strength).
Strength
Level
Strength Name
Specification
Keyword
Display
Mnemonic 7
Supply Drive
supply0
supply1
Su0
Su1 6
Strong Drive
strong0
strong1
St0
St1 5
Pull Drive
pull0
pull1
Pu0
Pu1 4
Large Capacitive
large
La0
La1 3
Weak Drive
weak0
weak1
We0
We1 2
Med. Capacitive
medium
Me0
Me1 1
Small Capacitive
small
Sm0
Sm1
High Impedance
highz0
highz1
HiZ0
HiZ1
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11. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.7 Literal Integer Numbers
Syntax: size'base value Sized integer in a specific radix (base)
size (optional) is the number of bits in the number. Unsized integers default to at least 32-bits.
'base (optional) represents the radix. The default base is decimal.
Base
Symbol
Legal Values
binary
b or B
0, 1, x, X, z, Z, ?, _
octal
o or O
0-7, x, X, z, Z, ?, _
decimal
d or D
0-9, _
hexadecimal
h or H
0-9, a-f, A-F, x, X, z, Z, ?, _
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12. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.7 Literal Integer Numbers
The ? is another way of representing the Z logic value.
An _ (underscore) is ignored (used to enhance readability).
Values are expanded from right to left (lsb to msb).
When size is less than value, the upper bits are truncated.
When size is larger than value, and the left-most bit of value is 0 or 1, zeros are left-extended to fill the size.
When size is larger than value, and the left-most bit of value is Z or X, the Z or X is left-extended to fill the size.
Examples 10
unsized
decimal
(32-bits)
'o7
octal
(32-bits)
1'b1
1 bit
binary 1
8'Hc5
8 bits
hex
6'hF0
6 bits
(truncated)
6'hF
(zero filled)
6'hZ
ZZZZZZ (Z filled)
Notes
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13. Verilog HDL Quick Reference Guide
4. Lexical Conventions
4.8 Literal Real Numbers
Syntax:
value.value decimal notation
baseEexponent scientific notation (the E is not case sensitive)
Real numbers are limited to the values 0-9 and underscore.
There must be a value on either side of the decimal point.
Examples
Notes
0.5
must have value on both sides of decimal point
3e4
3 times 104 (30000)
5.8E-3
5.8 times 10-3 (0.0058)
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14. Verilog HDL Quick Reference Guide
5. Module Definitions
Verilog HDL models are represented as modules.
Syntax:
Implicit Internal Connection (connects the port to an internal net or register of the same name )
module module_name (port_name, port_name, ... ); {module_items}
endmodule
Explicit Internal Connection (connects the port to an internal signal with a different name, or a bit select, part select, or concatenation of internal signals)
module module_name (.port_name (signal_name ), .port_name (signal_name ), ... );
{module_items}
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15. Verilog HDL Quick Reference Guide
5. Module Definitions
module_items are:
module port declarations
data type declarations
module instances
primitive instances
procedural blocks
continuous assignments
task definitions
function definitions
specify blocks
Module functionality may be:
Behavioral - modeled with procedural blocks or continuous assignment statements.
Structural - modeled as a netlist of module instances or primitive instances.
A combination of behavioral and structural.
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16. Verilog HDL Quick Reference Guide
5. Module Definitions
Module definitions may not be nested. Instead, modules instantiate other modules.
Module definitions may be expressed using parameter constants. Each instance of a module may redefine the parameters to be unique to that instance.
Module items may appear in any order, but port declarations and data type declarations should be listed before the ports or signals are referenced.
Verilog HDL Quick Reference Guide

17. 6. Module Port Declarations
Syntax:
port_direction [port_size] port_name, port_name,... ;
port_direction is declared as:
input for scalar or vector input ports.
output for scalar or vector output ports.
inout for scalar or vector bi-directional ports.
port_size is a range from [ msb : lsb ]
Examples
Notes
input a,b,sel;
3 scalar ports
output [7:0] result;
little endian convention
inout [0:15] data_bus;
big endian convention
input [15:12] addr;
msb:lsb may be any integer
parameter word = 32; input [word-1:0] addr;
constant expressions may be used
Verilog HDL Quick Reference Guide

18. 7. Data Type Declarations
Syntax:
register_type [size] variable_name , variable_name,...;
register_type [size] memory_name [array_size];
net_type [size] #(delay) net_name , net_name , ... ;
net_type (drive_strength) [size] #(delay) net_name = continuous_assignment ;
trireg (capacitance_strength) [size] #(delay, decay_time) net_name, net_name,...;
parameter constant_name = value,constant_name = value,...;
specparam constant_name = value,constant_name = value,...;
event event_name, event_name, ... ;
delay (optional) may only be specified on net data types.
size is a range from [msb : lsb].
array_size is from [ first_address : last_address]
strength (opt.) specified as (strength1,strength0) or _(strength0,strength1)
decay_time (opt.) The syntax is (rise_delay,fall_delay,decay_time)
Verilog HDL Quick Reference Guide

19. 7. Data Type Declarations
7.1 Register Data Types
Keyword
Functionality
reg
unsigned variable of any bit size
integer
signed 32-bit variable
time
unsigned 64-bit variable
real or realtime
double-precision floating point variable
Register data types are used as variables in procedural blocks.
Registers store logic values only (no logic strength).
A register data type must be used when the signal is on the left-hand side of a procedural assignment.
Verilog HDL Quick Reference Guide

20. 7. Data Type Declarations
7.2 Net Data Types
Keyword
Functionality
wire or tri
Simple interconnecting wire
wor or trior
Wired outputs OR together
wand or triand
Wired outputs AND together
tri0
Pulls down when tri-stated
tri1
Pulls up when tri-stated
supply0
Constant logic 0 (supply strength)
supply1
Constant logic 1 (supply strength)
trireg
Stores last value when tri-stated (capacitance strength)
Nets transfer both logic values and logic strengths.
A net data type must be used when a signal is driven by the output of some device; a signal is also declared as an input port or inout port; a signal is on the left-hand side of a continuous assignment.
Verilog HDL Quick Reference Guide

21. 7. Data Type Declarations
7.3 Other Data Types
Other Types
Functionality
parameter
Run-time constant for storing integers, real numbers, time, delays, or ASCII strings. Parameters may be redefined for each instance of a module.
specparam
Specify block constant for storing integers, real numbers, time, delays or ASCII strings
event
A momentary flag with no logic value or data storage. Often used for synchronizing concurrent activities within a module.
Verilog HDL Quick Reference Guide

22. 7. Data Type Declarations
7.4 Data Type Declaration Examples
Data Type Examples
Notes
wire a, b, c;
3 scalar nets
tri1 [7:0] data_bus;
8-bit net, pulls-up when tri-stated
reg [1:8] result;
an 8-bit unsigned variable
reg [7:0] RAM [0:1023];
a memory array; 8-bits wide, with 1K of addresses
wire #(2.4,1.8) carry;
a net with rise, fall delays
wire (strong1,pull0) sum = a+b;
net with drive strength and a continuous assignment
trireg (small) #(0,0,35) ram_bit;
net with small capacitance and 35 time unit decay time
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23. Verilog HDL Quick Reference Guide
8. Module Instances
Syntax:
Port Order Connections
module_name instance_name [instance_array_range] (signal, signal, ... );
Port Name Connections
module_name instance_name [instance_array_range] (.port_name(signal), (.port_name(signal), ...);
Explicit Parameter Redefinition
defparam heirarchy_path.parameter_name = value;
Implicit Parameter Redefinition
module_name #(value) instance_name (signals);
instance_name (required) is used to make multiple instances of the same module unique from one another.
instance_array_range (optional) instantiates multiple modules, each instance connected to separate bits of a vector.
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24. Verilog HDL Quick Reference Guide
8. Module Instances
Module Instance Examples
module reg4 (q,d,clock);
output [3:0] q;
input [3:0] d;
input clock;
wire [3:0] q, d;
wire clock;
//port order connection,
//2nd port not connected
dff u1 (q[0], , d[0], clock);
//port name connection,
//qb not connected
dff u2 (.clk(clock),.q(q[1]),.data(d[1]));
//explicit parameter redefine
dff u3 (q[2], ,d[2], clock);
defparam u3.delay = 3.2;
//implicit parameter redefine
dff #(2) u4 (q[3], , d[3], clock);
endmodule
module dff (q,qb,data,clk);
output q, qb;
input data, clk;
//default delay parameter
parameter delay = 1;
dff_udp #(delay) (q,data,clk);
not (qb, q);
endmodule
Verilog HDL Quick Reference Guide

25. Verilog HDL Quick Reference Guide
8. Module Instances
Array of Instances Examples
module tribuf64bit (out,in,enable);
output [63:0] out;
input [63:0] in;
input enable;
wire [63:0] out, in;
wire enable;
//array of 8 8-bit tri-state
//buffers;each instance is connected
//to 8-bit part selects of the 64-bit
//vectors;The scalar enable line is
//connected to all instances
tribuf8bit i[7:0] (out,in,enable);
endmodule
module tribuf8bit(out,in,enable);
output [7:0] y;
input [7:0] a;
input en;
wire [7:0] y, a;
wire en;
//array of 8 Verilog tri-state
//primitives each bit of the
//vectors is connected to a
//different primitive instance
bufif1 u[7:0] (y,a,en);
endmodule
Verilog HDL Quick Reference Guide

26. Verilog HDL Quick Reference Guide
9. Primitive Instances
Syntax
Gate Type
gate_type (drive_strength) #(delay) instance_name [instance_array_range] (terminal, terminal, ... );
Gate Type
Terminal Order
and or
xor
nand
nor
xnor
(1_output, 1-or-more_inputs)
buf
not
(1-or-more_outputs, 1_input)
bufif0 bufif1
notif0 notif1
(1_output, 1_input, 1_control)
pullup
pulldown
(1_output)
user-defined-primitives
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27. Verilog HDL Quick Reference Guide
9. Primitive Instances
Syntax
Switch Type
switch_type #(delay) instance_name [instance_array_range] (terminal, terminal, ... );
Switch Type
Terminal Order
pmos nmos
rpmos rnmos
(1_output, 1_input, 1_control)
cmos
rcmos
(1_output, 1_input, n_control, p_control)
tran
rtran
(2_bidirectional-inouts)
tranif0 rtranif0
rtranif1 rtranif1
(2_bidirectional-inouts, 1_control)
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28. Verilog HDL Quick Reference Guide
9. Primitive Instances
Primitive Delay Syntax
#delay or #(delay)
Single delay for all output transitions
#(delay, delay)
Separate delays for (rising, falling) transitions
#(delay, delay, delay)
Separate delays for (rising, falling, turn-off) transitions
#(min_delay:typ_delay:max_delay)
Minimum to maximum range of delays for all transitions
#(min_delay:typ_delay:max_delay, min_delay:typ_delay:max_delay)
Min. to max. range of delays for (rising, falling) transitions
#(min_delay:typ_delay:max_delay, min_delay:typ_delay:max_delay, min_delay:typ_delay:max_delay)
Min. to max. range of delays for (rising, falling, turn-off) transitions
Verilog HDL Quick Reference Guide

29. Primitive Instance Examples
9. Primitive Instances
Primitive Instance Examples
Notes
and i1 (out,in1,in2);
zero delay gate primitive
and #5 (o,i1,i2,i3,i4);
same delay for all transitions
not #(2,3) u7(out,in);
separate rise & fall delays
buf (pull0,strong1)(y,a);
output drive strengths model ECL
wire [31:0] y, a; buf #2.7 i[31:0] (y,a);
array of 32 buffers
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30. Verilog HDL Quick Reference Guide
10. Procedural Blocks
Syntax:
statement_group: group_name
local_variable_declarations
timing_control procedural_statements
end_of_statement_group
type_of_block is either initial or always:
initial procedural blocks process statements one time.
always procedural blocks process statements repeatedly.
statement_group--end_of_statement_group is used to group two or more procedural statements together and control the execution order:
begin--end groups two or more statements together sequentially.
fork--join groups two or more statements together in parallel.
Verilog HDL Quick Reference Guide

31. Procedural Block Examples
10. Procedural Blocks
Procedural Block Examples
Notes
initial
fork
bus = 16'h0000;
#10 bus = 16'hC5A5;
#20 bus = 16'hFFAA;
join
initial procedure executes statements one time;
The fork--join group places statements in parallel.
or b or ci)
begin
sum = a + b + ci;
end
always procedure executes statements repeatedly.
clk)
q <= data;
a statement group is not required when there is only one statement
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32. Verilog HDL Quick Reference Guide
10. Procedural Blocks
10.1 Timing Controls
#delay – delays execution for a specific amount of time. The delay may be a literal number, a variable, or an expression.
@(edge signal or edge signal or ... ) – Delays execution until there is a logic transition on a signal:
edge (optional) maybe either posedge or negedge. If no edge is specified, then any logic transition is used.
or is used to specify events on any of several signals.
signal may be scalar or vector, and any data type.
wait (expression) – Delays execution until the expression evaluates as true.
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33. Verilog HDL Quick Reference Guide
10. Procedural Blocks
10.2 Procedural Assignments
Blocking :
register_data_type = expression;
Non-blocking :
register_data_type <= expression;
Delayed :
timing_control register_data_type = expression;
timing_control register_data_type <= expression;
Blocking intra-delayed :
register_data_type = timing_control expression;
Non-blocking intra-delayed :
register_data_type <= timing_control expression;
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34. Verilog HDL Quick Reference Guide
10. Procedural Blocks
10.2 Procedural Assignments
Procedural continuous assignment :
assign register_data_type = expression;
De-activating a procedural continuous assignment :
deassign register_data_type;
Forcing any data type to a value :
force net_or_register_data_type = expression;
Removing the effect of a force :
release net_or_register_data_type;
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35. Verilog HDL Quick Reference Guide
10. Procedural Blocks
10.3 Programming Statements
If statement :
if (expression)
statement or statement_group
If-else statement :
if (expression)
statement or statement_group
else
Case statements:
case (net_or_register_or_literal)
case_match1: statement or statement_group
case_match2,
case_match3: statement or statement_group
default: statement or statement_group
endcase
casez (net_or_register_or_literal)
//a Z is logic value that represents don't-care bits.
casex (net_or_register_or_literal)
//Z or X are logic values that represent don't-care bits.
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36. Verilog HDL Quick Reference Guide
10. Procedural Blocks
10.3 Programming Statements
Loops:
forever statement or statement_group
repeat (number) statement or statement_group
while (expression) statement or statement_group
for (initial_assignment; expression; step_assignment) statement or statement_group
Discontinuing execution :
disable group_name;
Verilog HDL Quick Reference Guide

37. Verilog HDL Quick Reference Guide
10. Procedural Blocks
Procedural Statement Examples
//A 50 ns clock oscillator that starts after 1000 time units
initial
begin
clk = 0;
#1000 forever #25 clk = ~clk;
end
//Sensitivity list models sequential logic
clk)
begin
//Non-blocking assignments avoid race conditions in the byte swap
word[15:8]<= word[7:0];
word[7:0] <= word[15:8];
end
//Sensitivity list models combinational logic
or b or sel)
if (sel==0) y = a + b;
else y = a * b;
Verilog HDL Quick Reference Guide

38. 11. Operators Arithmetic Operators Bitwise Operators
m+n m-n –m m*n m/n m%n
Bitwise Operators
~m m&n m|n m^n m~^n m^~n
Unary Reduction Operators
&m ~&m|m ~|m ^m ~^m ^~m
Logical Operators
!m m&&n m||n
Equality Operators (compares logic values of 0 and 1)
m==n m!=n
Identity Operators (compares logic values of 0, 1, X and Z)
m===n m!==n
Relational Operators
m<n m>n m<=n m>=n
Logical Shift Operators
m<<n m>>n
Miscellaneous Operators
sel?m:n {m,n} {n{m}} ->m
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39. Verilog HDL Quick Reference Guide
11. Operators
! ~
* / %
<< >>
< <= > >=
== != === !==
& ~&
^ ~^
| ~|
&& || ?:
highest
(unary)
(binary)
precedence
lowest
Verilog HDL Quick Reference Guide

40. 12. Continuous Assignments
Syntax
Explicit Continuous Assignment
net_type [size] net_name;
assign #(delay) net_name = expression;
Implicit Continuous Assignment
net_type (strength) [size] net_name = expression;
Continuous Assignment Examples
//A 32-bit wide 2:1 MUX
wire [31:0] mux_out;
assign mux_out = sel? a : b;
//A 16-bit wide tri-state buffer with delay
tri [0:15] #2.8 buf_out = en? in: 16'bz;
//A 64-bit ALU with ECL output strengths
wire [63:0] (strong1,pull0) alu_out= alu_function(opcode,a,b);
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41. Verilog HDL Quick Reference Guide
13. Task Definitions
Syntax
task task_name;
input, output, and inout declarations
local variable declarations
procedural_statement or statement_group
endtask
Example of a Task
task read_mem; //TASK DEFINITION
input [15:0] address; //declaration order
output [31:0] data; // determines order
begin // of arguments when
read_request = 1; // task is called
wait (read_grant) addr_bus = address;
data = data_bus;
#5 addr_bus = 16'bz; read_request = 0;
end
endtask
read_mem(PC, IR); //TASK CALL
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42. Verilog HDL Quick Reference Guide
14. Function Definitions
Syntax
function [size_or_type] function_name;
input declarations
local variable declarations
procedural_statement or statement_group
endfunction
Example of a Function
function [7:0] GetByte; //FUNCTION DEFINITION
input [63:0] Word; //declaration order
input [3:0] ByteNum; //determines order
integer Bit; //of arguments when
reg [7:0] temp; //called
begin
for (Bit=0; Bit<=7; Bit=Bit+1)
temp[Bit] = Word[((ByteNum-1)*8)+Bit];
GetByte = temp; //A function returns
end // the value assigned
endfunction // to its name
this_byte = GetByte(data,4); //FUNCTION CALL
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43. Verilog HDL Quick Reference Guide
15. Specify Blocks
Syntax
specify
specparam_declarations
timing_constraint_checks
simple_pin-to-pin_path_delay
edge-sensitive_pin-to-pin_path_delay
state-dependent_pin-to-pin_path_delay
endspecify
15.1 Specparam Declarations
specparam param_name = value, param_name = value, ...;
specparams are constants used to store delays, delay calculation factors, synthesis factors, etc.
value may be integer, real, delay, or quoted string.
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44. Verilog HDL Quick Reference Guide
15. Specify Blocks
15.2 Timing Constraint Checks
$setup(data_event,reference_event,setup_limit,notifier);
$hold(reference_event,data_event,hold_limit, notifier);
$setuphold(reference_event,data_event,setup_limit,hold_limit, notifier);
$skew(reference_event,data_event,skew_limit,notifier);
$recovery(reference_event,data_event,limit,notifier);
$period(reference_event,period_limit,notifier);
$width(reference_event,width_limit,width_threshold,notifier);
The reference_event is an edge of an input signal that establishes a reference point for changes on the data event.
The data_event is the input signal that is monitored for changes.
The limit and threshold are delay values.
The notifier (optional) is a reg variable used as a flag.
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45. Verilog HDL Quick Reference Guide
15. Specify Blocks
15.3 Pin-to-pin Path Delays
Simple path delay statement:
(input_port polarity:path_token output_port) = (delay);
Edge-sensitive path delay:
(edge input_port path_token (output_port polarity:source)) = (delay);
State-dependent path delay:
if (first_condition) simple_or_edge-sensitive_path_delay
if (next_condition) simple_or_edge-sensitive_path_delay
ifnone simple_path_delay
path_token is either *> for full or => for parallel connection.
edge (optional) may be either posedge or negedge.
source (optional) is the input port or value the output will receive.
Verilog HDL Quick Reference Guide

46. Specify Block Examples
15. Specify Blocks
Specify Block Examples
(a => b) = 1.8; //parallel connection path; one delay for all output transitions
(a -*> b) = 2:3:4;/*full connection path; one min:typ:max delay range for all output transitions; b receives the inverted value of a */
specparam t1 = 3:4:6, //different path delays for rise, fall transitions
t2 = 2:3:4;
(a => y) = (t1,t2);
(a *> y1,y2) = (2,3,4,3,4,3);//different delays for 6 output transitions
(posedge clk => (qb -: d)) = (2.6, 1.8); /* edge-sensitive path delay; timing path is positive edge of clock to qb; qb receives the inverted value of data*/
if (rst && pst) (posedge clk=> (q +: d))=2;
//state-dependent edge sensitive path delay
if (opcode = 3'b000) // state-dependent path delays;
(a,b *> o) = 15; // an ALU with different delays for certain
if (opcode = 3'b001) // operations;
(a,b *> o) = 25;
ifnone (a,b *> o) = 10; // (default delay has no condition)
Verilog HDL Quick Reference Guide

47. 16. User Defined Primitives (UDPs)
Syntax
primitive primitive_name (output, input, input, ... );
output terminal_declaration;
input terminal_declaration;
reg output_terminal;
initial output_terminal = logic_value;
table
table_entry;
endtable
endprimitive
Combinational logic table entry:
input_logic_values : output_logic_value ;
Sequential logic table entry:
input_logic_values : previous_state : output_logic_value ;
Verilog HDL Quick Reference Guide

48. 16. User Defined Primitives (UDPs)
UDP Examples
primitive mux (y, a, b, sel); //COMBINATIONAL UDP
output y;
input sel, a, b;
table //table order for inputs matches primitive statement
// a b sel : y
0 ? 0 : 0; //select a; don't care about b
1 ? 0 : 1; //select a; don't care about b
? : 0; //select b; don't care about a
? : 1; //select b; don't care about a
endtable
endprimitive
Verilog HDL Quick Reference Guide

49. Verilog HDL Quick Reference Guide
16. User Defined Primitives (UDPs)
UDP Examples
primitive dff (q,d,clk,rst); //SEQUENTIAL UDP
output q;
input clk, rst, d;
reg q; //declaring output as reg defines
//sequential device with an internal
//storage state
initial q = 0; //powers up in reset state
table
// d clk rst:state:q
? ? 0 : ? :0; //low true reset
0 R 1 : ? :0; //clock in a 0
1 R 1 : ? :1: //clock in a 1
? N 1 : ? :-; //ignore negedge of clk
* ? 1 : ? :-; //ignore all edges on d
? ? P : ? :-; //ignore posedge of rst
0 (0X) 1 : 0 :-; //reduce pessimism
1 (0X) 1 : 1 :-; //reduce pessimism
endtable
endprimitive
Verilog HDL Quick Reference Guide