1. ECEN 301Discussion #23 – Sequential Logic1 DateDayClass No. TitleChaptersHW Due date Lab Due date Exam 19 NovWed23Sequential Logic14.1 20 NovThu 21 NovFri RecitationHW 9 22 NovSat 23 NovSun 24 NovMon24DAC15.4 25 NovTueRecitationHW 10 26 NovWedThanksgiving Schedule…

2. ECEN 301Discussion #23 – Sequential Logic2 Memory & Counters Exodus 12:14 14 And this day shall be unto you for a memorial; and ye shall keep it a feast to the LORD throughout your generations; ye shall keep it a feast by an ordinance for ever. D&C 107:100 100 He that is slothful shall not be counted worthy to stand, and he that learns not his duty and shows himself not approved shall not be counted worthy to stand. Even so. Amen.

3. ECEN 301Discussion #23 – Sequential Logic3 Lecture 23 – Combinational & Sequential Logic

4. ECEN 301Discussion #23 – Sequential Logic4 Digital Logic Hierarchy 2To4 FA D Mem n mm Intel Sequential Combinational Gates Transistors Processors

5. ECEN 301Discussion #23 – Sequential Logic5 Combinational Logic Decoders Multiplexers

6. ECEN 301Discussion #23 – Sequential Logic6 Decoders uDecode the input and signify its value by raising just one of its outputs. uA decoder with n inputs has 2 n outputs X Y Z W 2-to-4 Decoder AB W X Y Z DECODER Symbol

7. ECEN 301Discussion #23 – Sequential Logic7 Decoders uWrite the truth table X Y Z W

8. ECEN 301Discussion #23 – Sequential Logic8 Decoders uWrite the truth table X Y Z W ABWXYZ 001000 010100 100010 110001

9. ECEN 301Discussion #23 – Sequential Logic9 Multiplexors uConnect one of its inputs to its output according to select signals uUseful for selecting one from a collection of data inputs. uUsually has 2 n inputs and n select lines. AB S C 10 MULTIPLEXOR Symbol

10. ECEN 301Discussion #23 – Sequential Logic10 Multiplexors uWrite the truth table AB S C 10 MULTIPLEXOR Symbol ABSC 000? 001? 010? 011? 100? 101? 110? 111?

11. ECEN 301Discussion #23 – Sequential Logic11 Multiplexors uWrite the truth table AB S C 10 MULTIPLEXOR Symbol ABSC 0000 0010 0101 0110 1000 1011 1101 1111

12. ECEN 301Discussion #23 – Sequential Logic12 Sequential Logic

13. ECEN 301Discussion #23 – Sequential Logic13 Latches and Flip-Flops (FFs) Latch/FF: basic building block of memory devices 1.Bistable devices – remain in one of 2 states (logic 0 or logic 1) 2.Has 2 outputs (one is the complement of the other) – often only one is shown (the other is implied) Latches – imply that not controlled by a clock FFs – imply that they are controlled by a clock DQ CLK TQ J Q K D - FF JK - FF T - FF SQ R DQ E S Q R E D – Latch with enable SR – Latch with enable SR – Latch

14. ECEN 301Discussion #23 – Sequential Logic14 SR Latch SR Latch has 3 allowed states: ÙSet (set Q to 1): S = 1, R = 0 ÙReset (reset Q to 0): R = 1, S = 0 ÙPresent state (keep Q as is): S = 0, R = 0 SR Latch has 1 illegal state: ÙInstability (causes Q to switch between 0 and 1): S = 1, R = 1 S R Q Q SQ R SRQ new 00Q old 010 101 11X Present state Reset Set Illegal

15. ECEN 301Discussion #23 – Sequential Logic15 SR Latch Timing diagram: a graph of inputs and outputs over time. Time S R Q FF is setFF is reset FF is again reset FF is set HOLD SRQ new 00Q old 010 101 11X

16. ECEN 301Discussion #23 – Sequential Logic16 SR Latch SR Latch with additional inputs: ÙEnable (E) – S and R can only change Q when E is 1 ÙPreset (PRE) – regardless of S, R, or E, put Q to 1 when PRE is 1 ÙClear (CLR) – regardless of S, R, E, or PRE, put Q to 0 when CLR is 1 SQ R E PRE CLR E S R PRE CLR Q Precedence : 1.If CLR = 1, Q = 0 2.If PRE = 1, Q = 1 3.If E = 1, Q is set based on SR a)If S = 0 and R = 0, Q = hold b)If S = 0 and R = 1, Q = 0 c)If S = 1 and R = 0, Q = 1 d)If S = 1 and R = 1, Q = unstable 4.Else Q is held SR can only change Q only in blue regions (where E = 1)

17. ECEN 301Discussion #23 – Sequential Logic17 D Latch D Latch has only 2 states: ÙSet (set Q to 1): D = 1 ÙReset (reset Q to 0): D = 0 D Latch with enable (E): ÙQ can only change when E = 1 EDQ new 00Q old 01 100 111 DQ E SQ R E D E E D Q D can only change Q only in blue regions (where E = 1)

18. ECEN 301Discussion #23 – Sequential Logic18 D Flip-Flop D FF: 2 SR latches in master/slave configuration. The output (Q) changes on the rising clock edge DCLKQ new 00 11 DQ CLK SQ R SQ RQ E E D Q MasterSlave CLK D Q D can only change Q only on rising clock edge (arrows) “Edge-Triggered”

19. ECEN 301Discussion #23 – Sequential Logic19 JK Flip-Flop JK FF: 2 SR latches in master/slave configuration. The output (Q) changes on the falling clock edge JKCLKQ new 00Q old 010 101 11 JK FF has 4 allowed states: ÙPresent state (keep Q as is): J = 0, K = 0 ÙReset (reset Q to 0): J = 0, K = 1 ÙSet (set Q to 1): J = 1, K = 0 ÙToggle (set Q to Q): J = 1, K = 1 SQ R SQ RQ E E CLK J Q QK J Q K Indicates falling clock edge

20. ECEN 301Discussion #23 – Sequential Logic20 T Flip-Flop T FF: JK FF with J and K inputs connected TCLKQ new 0Q old 1 T FF has 2 allowed states: ÙPresent state (keep Q as is): T = 0 ÙToggle (set Q to Q): T = 1 CLK T Q J Q K TQ

21. ECEN 301Discussion #25 – Final Review21 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK TQ J Q K DQ Q2Q2 Q1Q1 Q0Q0

22. ECEN 301Discussion #25 – Final Review22 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK T Q new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 000 0 0 0 0 1 1 1 0 1.Set outputs to 000 2.Based on output values change FF inputs 3.On each clock cycle: a)change FF outputs based on inputs b)Change FF inputs based on new outputs TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0

23. ECEN 301Discussion #25 – Final Review23 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 000 0 0 0 0 1 1 1 0 Inputs changed due to outputs TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0

24. ECEN 301Discussion #25 – Final Review24 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 111 0 0 0 0 1 1 1 0 Outputs change on new clock cycle TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0

25. ECEN 301Discussion #25 – Final Review25 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 111 1 1 1 1 0 0 0 1 Inputs changed due to outputs TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0

26. ECEN 301Discussion #25 – Final Review26 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 2010 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 010 1 1 1 1 0 0 0 1 Outputs change on new clock cycle TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0

27. ECEN 301Discussion #25 – Final Review27 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 2010 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 010 0 0 1 0 1 0 1 0 TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0 Inputs changed due to outputs

28. ECEN 301Discussion #25 – Final Review28 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 2010 3100 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 100 0 0 1 0 1 0 1 0 TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0 Outputs change on new clock cycle

29. ECEN 301Discussion #25 – Final Review29 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 2010 3100 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 100 1 0 0 1 1 0 0 0 TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0 Inputs changed due to outputs

30. ECEN 301Discussion #25 – Final Review30 Flip-Flops Example: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles CLK CycleQ2Q2 Q1Q1 Q0Q0 start000 1111 2010 3100 4110 TCLKQ new 0Q old 1 DCLKQ new 00 11 JKCLKQ new 00Q old 010 101 11 110 1 0 0 1 1 0 0 0 TQ CLK J Q K DQ Q2Q2 Q1Q1 Q0Q0 Outputs change on new clock cycle

31. ECEN 301Discussion #23 – Sequential Logic31 Digital Counters Binary up counter: with N bits, cycles through the numbers from 0 to 2 N – 1 ÙA reset input will force the output to be zero N-bit Binary Counter B N-1 B0B0 B1B1 B2B2 … CLK Reset 3-bit up-counter CLK B0B0 B1B1 B2B2 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1

32. ECEN 301Discussion #23 – Sequential Logic32 Digital Counters Ripple counter: with N bits, cycles through the numbers from 0 to 2 N – 1 ÙN JK FFs cascaded together to produce an N-bit up counter CLK J Q K J Q K J Q K 111 B0B0 B1B1 B2B2 NB: for 3-bit counter we need 3 FFs CLK B0B0 B1B1 B2B2

33. ECEN 301Discussion #23 – Sequential Logic33 Digital Counters Synchronous counter: with N bits, cycles through the numbers from 0 to 2 N – 1 ÙInput clock drives all FFs simultaneously TQ CLK TQ TQ 1 B0B0 B1B1 B2B2 B0B0 B1B1 B2B2

34. ECEN 301Discussion #23 – Sequential Logic34 Registers Register : an N-bit register is a cascade of N FFs to store data. ÙSimplest type is a parallel input, parallel output register ÙRead/Write (WR) signal determines if data on the input is written to the FFs If WR = 1 data is written DQ CLK WR DQ CLK WR DQ CLK WR CLK Read/Write Q0Q0 Q1Q1 Q N-1 D0D0 D1D1 D2D2 Register N N CLK WR

35. ECEN 301Discussion #23 – Sequential Logic35 Simple Memory 2-to-4 Decoder a1a0 00 01 10 11 Register WR read/writed input q output This is a functional view. The key parts are: address decoder memory cells (registers) output selector (mux) address Memory q n WR d mm MEMORY Symbol n = 2 address q0q0 q1q1 q2q2 q3q3 addr