1. CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 10: Digital System Design
Chapter 10

2. Digital System Design Digital system consists of two parts:
Datapath circuit – used to store, manipulate, and transfer date.
Control circuit – controls the operation of the datapath. Usually its built using an FSM.

3. Figure 10.1 A flip-flop with an enable inputD Q Q R 1
Clock Q
Figure A flip-flop with an enable input

4. Figure 10.2 VHDL code for a D flip-flop with an enable input
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY rege IS
PORT ( R, Resetn, E, Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC ) ;
END rege ;
ARCHITECTURE Behavior OF rege IS
BEGIN
PROCESS ( Resetn, Clock )
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
IF E = '1' THEN
Q <= R ;
ELSE
Q <= Q ;
END IF ;
END PROCESS ;
END Behavior ;
Figure VHDL code for a D flip-flop with an enable input

5. Figure 10.3 VHDL code for an n-bit register with an enable input
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regne ;
ARCHITECTURE Behavior OF regne IS
BEGIN
PROCESS ( Resetn, Clock )
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
IF E = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END Behavior ;
Figure VHDL code for an n-bit register with an enable input

6. USE ieee.std_logic_1164.all ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
L, E, w : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftlne ;
ARCHITECTURE Behavior OF shiftlne IS
BEGIN
PROCESS
… con’t
Figure 10.4a Code for a right-to-left shift register with an enable input

7. WAIT UNTIL Clock'EVENT AND Clock = '1' ;
… con’t
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF E = '1' THEN
IF L = '1' THEN
Q <= R ;
ELSE
Q(0) <= w ;
Genbits: FOR i IN 1 TO N-1 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 10.4b Code for a right-to-left shift register with an enable input (con’t)

8. Figure 10.5a Component declaration statements for building blocks
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- 2-to-1 multiplexer
COMPONENT mux2to1
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
-- D flip-flop with 2-to-1 multiplexer connected to D
COMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
-- n-bit register with enable
COMPONENT regne
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
… con’t
Figure 10.5a Component declaration statements for building blocks

9. -- n-bit right-to-left shift register with parallel load and enable
… con’t
-- n-bit right-to-left shift register with parallel load and enable
COMPONENT shiftlne
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
L, E, w : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;
-- n-bit left-to-right shift register with parallel load and enable
COMPONENT shiftrne
Figure 10.5b Component declaration statements for building blocks (con’t)

10. -- up-counter that counts from 0 to modulus-1 COMPONENT upcount
… con’t
-- up-counter that counts from 0 to modulus-1
COMPONENT upcount
GENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Resetn : IN STD_LOGIC ;
Clock, E, L : IN STD_LOGIC ;
R : IN INTEGER RANGE 0 TO modulus-1 ;
Q : BUFFER INTEGER RANGE 0 TO modulus-1 ) ;
END COMPONENT ;
-- down-counter that counts from modulus-1 down to 0
COMPONENT downcnt
PORT ( Clock, E, L : IN STD_LOGIC ;
END components ;
Figure 10.5c Component declaration statements for building blocks (con’t)

11. Static Random Access Memory
SRAM is used when a large amount of data needs to be stored.
SRAM block is 2-dimensional array of SRAM cells where each cell stores 1-bit.
To store m elements of n-bits, the aspect ratio of the SRAM array would be m  n.

12. Sel
Data
Figure An SRAM cell

13. Figure 10.7 A 2 x 2 array of SRAM cells
Data
Data 1
Sel
Sel 1
Figure A 2 x 2 array of SRAM cells

14. Figure 10.8 A 2m x n SRAM block Data inputs d d d Write Sel Sel a Sel– 1 n – 2
Write
Sel
Sel 1 a
Sel 2
decoder a 1
Address m
-to-2 a m – 1 m
Sel 2 m ” 1
Read
Data outputs q q q n – 1 n – 2
Figure A 2m x n SRAM block

15. Figure 10.9 Pseudo-code for the bit counter= ;
while A  do if a 1
then +
End if;
Right-shift
End while;
Figure Pseudo-code for the bit counter

16. Figure 10.10 ASM chart for the bit counter
Reset S1
Load A B 1 s s 1 S2 S3
Shift right A
Done 1 B B + 1 A = ? a 1
Figure ASM chart for the bit counter

17. Figure 10.11 Data path for the bit countern
log n 2 w LB L LA L
Shift EB E
Counter EA E
Clock
log n A 2 n z a B
Figure Data path for the bit counter

18. Figure 10.12 ASM chart for the bit counter control circuit
Reset S1 LB , EB EA 1 1 LA s s 1 S2 S3 EA
Done 1 EB z a 1
Figure ASM chart for the bit counter control circuit

19. Figure 10.13a VHDL code for the bit-counting circuit
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY work ;
USE work.components.shiftrne ;
ENTITY bitcount IS
PORT( Clock, Resetn : IN STD_LOGIC ;
LA, s : IN STD_LOGIC ;
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
B : BUFFER INTEGER RANGE 0 to 8 ;
Done : OUT STD_LOGIC ) ;
END bitcount ;
ARCHITECTURE Behavior OF bitcount IS
TYPE State_type IS ( S1, S2, S3 ) ;
SIGNAL y : State_type ;
SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL z, EA, LB, EB, low : STD_LOGIC ;
BEGIN
FSM_transitions: PROCESS ( Resetn, Clock )
IF Resetn = '0' THEN
y <= S1 ;
… con’t
Figure 10.13a VHDL code for the bit-counting circuit

20. Figure 10.13b VHDL code for the bit-counting circuit (con’t)
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM_outputs: PROCESS ( y, s, A(0), z )
BEGIN
EA <= '0' ; LB <= '0' ; EB <= '0' ; Done <= '0' ;
LB <= '1' ; EB <= '1' ;
IF s = '0' AND LA = '1' THEN EA <= '1' ;
ELSE EA <= '0' ; END IF ;
EA <= '1' ;
IF A(0) = '1' THEN EB <= '1' ; ELSE EB <= '0' ; END IF ;
… con’t
Figure 10.13b VHDL code for the bit-counting circuit (con’t)

21. Figure 10.13c VHDL code for the bit-counting circuit (con’t)
WHEN S3 =>
Done <= '1' ;
END CASE ;
END PROCESS ;
-- The datapath circuit is described below
upcount: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
B <= 0 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF EB = '1' THEN
IF LB = '1' THEN
ELSE
B <= B + 1 ;
END IF ;
END IF;
END PROCESS;
low <= '0' ;
ShiftA: shiftrne GENERIC MAP ( N => 8 )
PORT MAP ( Data, LA, EA, low, Clock, A ) ;
z <= '1' WHEN A = " " ELSE '0' ;
END Behavior ;
Figure 10.13c VHDL code for the bit-counting circuit (con’t)

22. Figure 10.14 Simulation results for the bit-counting circuit

23. Figure 10.15 An algorithm for multiplication
Decimal
Binary 13 1 1 1
Multiplicand 11 1 1 1
Multiplier 13 13 1 1 1
143 1 1 1 1
Product
(a)
Manual
method P = ;
for i to n 1 do if b
then + A
end
if;
Left-shift
for; –
(b)
Pseudo-code
Figure An algorithm for multiplication

24. Figure 10.16 ASM chart for the multiplier
Reset S1
Load A P
Load B 1 s s 1 S2 S3
Shift left A ,
Shift right B
Done 1 P P + A B = ? b 1
Figure ASM chart for the multiplier

25. Figure 10.17 Datapath circuit for the multiplier
DataA LA EA A
Clock P
DataP
Register EP
Sum z B b
DataB LB EB + 2n n
Shift-left
register
Shift-right
Psel 1
Figure Datapath circuit for the multiplier

26. Figure 10.18 ASM chart for the multiplier control circuitEP z b
Reset S3 1 s
Done
Psel = , S1 S2 LA EA LB EB
EAEB
Figure ASM chart for the multiplier control circuit

27. Figure 10.19a VHDL code for the multiplier circuit
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY multiply IS
GENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;
PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;
LA, LB, s : IN STD_LOGIC ;
DataA : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
DataB : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
P : BUFFER STD_LOGIC_VECTOR(NN-1 DOWNTO 0) ;
Done : OUT STD_LOGIC ) ;
END multiply ;
ARCHITECTURE Behavior OF multiply IS
TYPE State_type IS ( S1, S2, S3 ) ;
SIGNAL y : State_type ;
SIGNAL Psel, z, EA, EB, EP, Zero : STD_LOGIC ;
SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN-1 DOWNTO 0) ;
BEGIN
… con’t
Figure 10.19a VHDL code for the multiplier circuit

28. Figure 10.19b VHDL code for the multiplier circuit (con’t)
FSM_transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM_outputs: PROCESS ( y, s, LA, LB, B(0) )
EP <= '0' ; EA <= '0' ; EB <= '0' ; Done <= '0' ; Psel <= '0';
EP <= '1' ;
IF s = '0' AND LA = '1' THEN EA <= '1' ;
ELSE EA <= '0' ; END IF ;
IF s = '0' AND LB = '1' THEN EB <= '1' ;
… con’t
Figure 10.19b VHDL code for the multiplier circuit (con’t)

29. Figure 10.19c VHDL code for the multiplier circuit (con’t)
ELSE EB <= '0' ; END IF ;
WHEN S2 =>
EA <= '1' ; EB <= '1' ; Psel <= '1' ;
IF B(0) = '1' THEN EP <= '1' ; ELSE EP <= '0' ; END IF ;
WHEN S3 =>
Done <= '1' ;
END CASE ;
END PROCESS ;
-- Define the datapath circuit
Zero <= '0' ; N_Zeros <= (OTHERS => '0' ) ;
Ain <= N_Zeros & DataA ;
ShiftA: shiftlne GENERIC MAP ( N => NN )
PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ;
ShiftB: shiftrne GENERIC MAP ( N => N )
PORT MAP ( DataB, LB, EB, Zero, Clock, B ) ;
z <= '1' WHEN B = N_Zeros ELSE '0' ;
Sum <= A + P ;
-- Define the 2n 2-to-1 multiplexers for DataP
GenMUX: FOR i IN 0 TO NN-1 GENERATE
Muxi: mux2to1 PORT MAP ( Zero, Sum(i), Psel, DataP(i) ) ;
END GENERATE;
RegP: regne GENERIC MAP ( N => NN )
PORT MAP ( DataP, Resetn, EP, Clock, P ) ;
END Behavior ;
Figure 10.19c VHDL code for the multiplier circuit (con’t)

30. Figure 10.20 Simulation results for the multiplier circuit

31. Figure 10.21 An algorithm for division15 Q 9
140 B
1001
100
01100 A 9
1001 50 10
001 45 10 01 5
10000
1001
1110
1001
(a) An example using decimal numbers
101 R
(b) Using binary numbers R = ;
for i = to n – 1 do
Left-shift R
A ; if R 
B then q = 1 ; i R = R – B ;
else q = ; i
end
if;
end
for;
(c)
Pseudo-code
Figure An algorithm for division

32. Figure 10.22 ASM chart for the dividerB ? C n 1 – , s S1 S2
Load A
Load B
Shift left R||A ”
Shift 0 into Q
Shift 1 into Q = S3
Reset
Done S4
Figure ASM chart for the divider

33. Figure 10.23 Datapath circuit for the dividern LA
DataA
DataB EB
Rsel 1 n n LR L
Left-shift L
Left-shift E ER E w EA
Register
register E
register n n n a B n ” 1 A EQ E
Left-shift w c c 1
register
out in + n n
Clock Q R
Figure Datapath circuit for the divider

34. Figure 10.24 ASM chart for the divider control circuit
Rsel =
LR, ER, LC, EC , s 1 S1 S2
Done
EQ, Rsel EC
LR, ER S4 S3
Reset LA EA
ER, EA c
out z
Figure ASM chart for the divider control circuit

35. Figure 10.25 An example of division using n = 8 clock cyclesB
1001 A
Clock cycle R rr A/ Q
Load A, B 1 1 1
Shift left 1 1 1 1
Shift left , Q 1 1 1 2
Shift left , Q 1 1 1 3
Shift left , Q 1 1 1 4
Shift left , Q 1 1 1 5
Subtract , Q 1 1 1 1 6
Subtract , Q 1 1 1 1 7
Subtract , Q 1 1 1 1 1 1 1 , 8
Subtract Q 1 1 1 1 1 1 1
Figure An example of division using n = 8 clock cycles

36. Figure 10.26 An example of division using n = 8 clock cycles
Rsel = LC EC ER , s 1 S1 S2 LR
Reset
EA, ER0 c
out z
ER0 EA LA
Done S3
Figure An example of division using n = 8 clock cycles

37. Figure 10.27 Datapath circuit for the enhanced dividerL
DataB LR ER
Clock
Register EB R
DataA LA EA + c
out in 1 B w
Rsel n
Left-shift
register q – Q D
ER0 r 2 rr
Figure Datapath circuit for the enhanced divider

38. Figure 10.28a VHDL code for the divider circuit
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;
s, LA, EB : IN STD_LOGIC ;
DataA : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
DataB : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
R, Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Done : OUT STD_LOGIC ) ;
END divider ;
ARCHITECTURE Behavior OF divider IS
TYPE State_type IS ( S1, S2, S3 ) ;
SIGNAL y : State_type ;
SIGNAL Zero, Cout, z : STD_LOGIC ;
SIGNAL EA, Rsel, LR, ER, ER0, LC, EC, R0 : STD_LOGIC ;
SIGNAL A, B, DataR : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
SIGNAL Sum : STD_LOGIC_VECTOR(N DOWNTO 0) ; -- adder outputs
SIGNAL Count : INTEGER RANGE 0 TO N-1 ;
… con’t
Figure 10.28a VHDL code for the divider circuit

39. Figure 10.28b VHDL code for the divider circuit (con’t)
BEGIN
FSM_transitions: PROCESS ( Resetn, Clock )
IF Resetn = '0' THEN y <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM_outputs: PROCESS ( s, y, Cout, z )
LR <= '0' ; ER <= '0' ; ER0 <= '0' ;
LC <= '0' ; EC <= '0' ; EA <= '0' ; Done <= '0' ;
Rsel <= '0' ;
… con’t
Figure 10.28b VHDL code for the divider circuit (con’t)

40. Figure 10.28c VHDL code for the divider circuit (con’t)
LC <= '1' ; EC <= '1' ; ER <= '1' ;
IF s = '0' THEN
LR <= '1' ;
IF LA = '1' THEN EA <= '1' ; ELSE EA <= '0' ; END IF ;
ELSE
EA <= '1' ; ER0 <= '1' ;
END IF ;
WHEN S2 =>
Rsel <= '1' ; ER <= '1' ; ER0 <= '1' ; EA <= '1' ;
IF Cout = '1' THEN LR <= '1' ; ELSE LR <= '0' ; END IF ;
IF z = '0' THEN EC <= '1' ; ELSE EC <= '0' ; END IF ;
WHEN S3 =>
Done <= '1' ;
END CASE ;
END PROCESS ;
-- define the datapath circuit
Zero <= '0' ;
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, EB, Clock, B ) ;
ShiftR: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataR, LR, ER, R0, Clock, R ) ;
… con’t
Figure 10.28c VHDL code for the divider circuit (con’t)

41. Figure 10.28d VHDL code for the divider circuit (con’t)
FF_R0: muxdff PORT MAP ( Zero, A(N-1), ER0, Clock, R0 ) ;
ShiftA: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataA, LA, EA, Cout, Clock, A ) ;
Q <= A ;
Counter: downcnt GENERIC MAP ( modulus => N )
PORT MAP ( Clock, EC, LC, Count ) ;
z <= '1' WHEN Count = 0 ELSE '0' ;
Sum <= R & R0 + (NOT B +1) ;
Cout <= Sum(N) ;
DataR <= (OTHERS => '0') WHEN Rsel = '0' ELSE Sum ;
END Behavior ;
Figure 10.28d VHDL code for the divider circuit (con’t)

42. Figure 10.29 Simulation results for the divider circuit

43. Figure 10.30 An algorithm for finding the mean of k numbers
Sum = ;
for i k 1
down to do
+R ;
end
for; M ÷
(a)
Pseudo-code
(b)
ASM
chart C – , s S1 S2
Done
Reset R + S4 ? S3
Load registers
Figure An algorithm for finding the mean of k numbers

44. Figure 10.31 Datapath circuit for the mean operation

45. Figure 10.32 ASM chart for the control circuit

46. Figure 10.33 Schematic of the mean circuit with an SRAM block

47. Figure 10.34 Simulation results for the mean circuit using SRAM

48. Figure 10.35 Pseudo-code for the sort operation= to k – 2 do A = R ; i
for j = i + 1 to k – 1 do B = R ; j if B
< A
then R = B ; i R = A ; j A = R ; i
end if ;
end for;
end for;
Figure Pseudo-code for the sort operation

49. Figure 10.36 ASM chart for the sort operationB A
< ? C i s 1 S1 S2
Done
Reset R j , + S4 S5 S3 k – = 2
Load registers S9 S7 S6 S8
Figure ASM chart for the sort operation

50. Figure 10.37 A part of the datapath circuit for the sort operation
DataIn
ABmux n 1
WrInit n
RData
Rin E
Rin E
Rin E
Rin E 1 2 3 R R R R 1 2 3 1 2 3
Imux
ABData
Ain E
Bin E Rd n
Clock
DataOut 1
Bout
< A B
BltA
Figure A part of the datapath circuit for the sort operation

51. Figure 10.38 A part of the datapath circuit for the sort operation2 2 LI L R LJ L R EI E
Counter EJ E
Counter Q Q C C i j
Clock 2 = k – 2 z i 2
Csel 1 =
k – 1 z j
Cmux 2 2
RAdd
Int 1
Imux 2 y
Rin w , w 1 y 1
Rin 1 y 2
Rin
WrInit 2 En y
Rin Wr 3 3
2-to-4 decoder
Figure A part of the datapath circuit for the sort operation

52. Figure 10.39 ASM chart for the control circuit
Csel =
Int 1
Ain , Wr
Bout
Aout
Bin s S1 S2
Done
Reset S4 S5 S3 S9 S7 S6 S8 LI EI LJ EJ
BltA z j i
Figure ASM chart for the control circuit

53. Figure 10.40a VHDL code for the sort operation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.components.all ;
ENTITY sort IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( Clock, Resetn : IN STD_LOGIC ;
s, WrInit, Rd : IN STD_LOGIC ;
DataIn : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
DataOut : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Done : BUFFER STD_LOGIC ) ;
END sort ;
ARCHITECTURE Behavior OF sort IS
TYPE State_type IS ( S1, S2, S3, S4, S5, S6, S7, S8, S9 ) ;
SIGNAL y : State_type ;
SIGNAL Ci, Cj : INTEGER RANGE 0 TO 3 ;
SIGNAL Rin : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
TYPE RegArray IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
SIGNAL R : RegArray ;
SIGNAL RData, ABMux : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
SIGNAL Int, Csel, Wr, BltA : STD_LOGIC ;
SIGNAL CMux, IMux : INTEGER RANGE 0 TO 3 ;
Figure 10.40a VHDL code for the sort operation

54. Figure 10.40b VHDL code for the sort operation (con’t)
SIGNAL Ain, Bin, Aout, Bout : STD_LOGIC ;
SIGNAL LI, LJ, EI, EJ, zi, zj : STD_LOGIC ;
SIGNAL Zero : INTEGER RANGE 3 DOWNTO 0 ; -- parallel data for Ci = 0
SIGNAL A, B, ABData : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
BEGIN
FSM_transitions: PROCESS ( Resetn, Clock )
IF Resetn = '0' THEN
y <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 => IF S = '0' THEN y <= S1 ;
ELSE y <= S2 ; END IF ;
WHEN S2 => y <= S3 ;
WHEN S3 => y <= S4 ;
WHEN S4 => y <= S5 ;
WHEN S5 => IF BltA = '1' THEN y <= S6 ; ELSE y <= S8 ; END IF ;
WHEN S6 => y <= S7 ;
WHEN S7 => y <= S8 ;
WHEN S8 =>
IF zj = '0' THEN y <= S4 ;
ELSIF zi = '0' THEN y <= S2 ;
ELSE y <= S9 ;
END IF ;
Figure 10.40b VHDL code for the sort operation (con’t)

55. Figure 10.40c VHDL code for the sort operation (con’t)
WHEN S9 => IF s = '1' THEN y <= S9 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
-- define the outputs generated by the FSM
Int <= '0' WHEN y = S1 ELSE '1' ;
Done <= '1' WHEN y = S9 ELSE '0' ;
FSM_outputs: PROCESS ( y, zi, zj )
BEGIN
LI <= '0' ; LJ <= '0' ; EI <= '0' ; EJ <= '0' ; Csel <= '0' ;
Wr <= '0'; Ain <= '0' ; Bin <= '0' ; Aout <= '0' ; Bout <= '0' ;
CASE y IS
WHEN S1 => LI <= '1' ; EI <= '1' ;
WHEN S2 => Ain <= '1' ; LJ <= '1' ; EJ <= '1' ;
WHEN S3 => EJ <= '1' ;
WHEN S4 => Bin <= '1' ; Csel <= '1' ;
WHEN S5 => -- no outputs asserted in this state
WHEN S6 => Csel <= '1' ; Wr <= '1' ; Aout <= '1' ;
WHEN S7 => Wr <= '1' ; Bout <= '1' ;
WHEN S8 => Ain <= '1' ;
IF zj = '0' THEN
EJ <= '1' ;
ELSE
EJ <= '0' ;
Figure 10.40c VHDL code for the sort operation (con’t)

56. Figure 10.40d VHDL code for the sort operation (con’t)
IF zi = '0' THEN
EI <= '1' ;
ELSE
EI <= '0' ;
END IF;
END IF ;
WHEN S9 => -- Done is assigned 1 by conditional signal assignment
END CASE ;
END PROCESS ;
-- define the datapath circuit
Zero <= 0 ;
GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )
PORT MAP ( RData, Resetn, Rin(i), Clock, R(i) ) ;
END GENERATE ;
RegA: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Ain, Clock, A ) ;
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Bin, Clock, B ) ;
BltA <= '1' WHEN B < A ELSE '0' ;
ABMux <= A WHEN Bout = '0' ELSE B ;
RData <= ABMux WHEN WrInit = '0' ELSE DataIn ;
OuterLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EI, LI, Zero, Ci ) ;
Figure 10.40d VHDL code for the sort operation (con’t)

57. Figure 10.40e VHDL code for the sort operation (con’t)
InnerLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EJ, LJ, Ci, Cj ) ;
CMux <= Ci WHEN Csel = '0' ELSE Cj ;
IMux <= Cmux WHEN Int = '1' ELSE Radd ;
WITH IMux Select
ABData <= R(0) WHEN 0,
R(1) WHEN 1,
R(2) WHEN 2,
R(3) WHEN OTHERS ;
RinDec: PROCESS ( WrInit, Wr, IMux )
BEGIN
IF (WrInit OR Wr) = '1' THEN
CASE IMux IS
WHEN 0 => Rin <= "0001" ;
WHEN 1 => Rin <= "0010" ;
WHEN 2 => Rin <= "0100" ;
WHEN OTHERS => Rin <= "1000" ;
END CASE ;
ELSE Rin <= "0000" ; END IF ;
END PROCESS ;
Zi <= '1' WHEN Ci = 2 ELSE '0' ;
Zj <= '1' WHEN Cj = 3 ELSE '0' ;
DataOut <= (OTHERS => 'Z') WHEN Rd = '0' ELSE ABData ;
END Behavior ;
Figure 10.40e VHDL code for the sort operation (con’t)

58. Figure 10.41a Simulation results for the sort operation

59. Figure 10.41b Simulation results for the sort operation

60. Figure 10.42 Using tri-state buffers in the datapath circuit
DataIn n
WrInit n
Rin E
Rin E
Rin E
Rin E 1 2 3
Rout
Rout
Rout
Rout 1 2 3 n n n n
Ain E
Bin E n
Clock A n B n
Aout Rd
<
DataOut
Bout
BltA
Figure Using tri-state buffers in the datapath circuit

61. Figure 10.43 Clock enable circuit
Data D Q
Clock Q E
Figure Clock enable circuit

62. Figure 10.11 Data path for the bit countern
log n 2 w LB L LA L
Shift EB E
Counter EA E
Clock
log n A 2 n z a B
Figure Data path for the bit counter

63. Figure 10.44 An H tree clock distribution networkff ff ff ff ff ff ff ff
Clock ff ff ff ff ff ff ff ff
Figure An H tree clock distribution network

64. Figure 10.45 A flip-flop in an integrated circuit
Data
Chip package pin
Data A D Q
Out B
Clock t t
Clock od
Figure A flip-flop in an integrated circuit

65. Figure 10.46 Flip-flop timing in a chip

66. Asynchronous Inputs to FFs
Inputs generated asynchronously may violate setup and hold times of flip-flops.
FF may take on a value between 0 and 1.
This condition is called a metastable state.
There is no guarantee of how long the circuit will persist in this state.
Care must be taken to reduce the probability of having synchronization failure.

67. Figure 10.47 Asynchronous inputs
Data
Data D Q D Q
(asynchronous)
(synchronous)
Clock Q Q
Figure Asynchronous inputs

68. Figure 10.48 Switch debouncing circuitV DD R V DD S
Data R
Data R R
(a) Single-pole single-throw switch V DD
(b) Single-pole double-throw switch with a basic SR latch
Figure Switch debouncing circuit