PROGRAMMABLE LOGIC DESIGN WITH VHDL

PROGRAMMABLE LOGIC DESIGN WITH VHDL
Emphasize that the class will emphasize VHDL and hands-on exercises geared to VHDL design. Emphasize that this is intended as an introductory class. Emphasize that we will learn how to use the Warp tools so we can do the exercises. PROGRAMMABLE LOGIC DESIGN WITH VHDL

Objectives Upon completion of this training, your VHDL knowledge will enable you to: Implement efficient combinatorial and sequential logic Design state machines and understand implementation trade-offs Use hierarchy / Create reusable components Identify how VHDL will synthesize and fit into a PLD or CPLD This is what they will learn about VHDL

Agenda Introduction, Why Use VHDL? PLD Design Flow
VHDL Design Descriptions The Entity, Ports, Modes, Types Exercise #1 The Architecture, Architecture Styles VHDL Statements, Combinational Logic Processes, Signals vs. Variables VHDL Operators/Overloading/Inferencing Tri-State Logic, Don't Cares VHDL Identifiers Exercise #2, Exercise #3 Registers/Sequential Logic Wait Statement, Implicit Memory Exercise #4 - Lunch State Machines and State Encoding Exercise #5 Hierarchy (components, packages, and libraries) Exercise #6 Generate Statement Multiplexing I/O pins Exercise #7 Attributes, Miscellaneous Topics, Wrap-up exercise 1 should take less than 15 minutes exercise 2 should take about the same amount of time exercise 3 takes nearly an hour exercise 4 takes 45 minutes to an hour. You might consider giving the solution after lunch. exercises 5 and 6 take about 45 minutes each exercise 7 doesn’t add much to the party so you may just want to leave that as an “exercise for the student”

Introduction VHDL is used to: document circuits simulate circuits
synthesize design descriptions Synthesis is the reduction of a design description to a lower-level representation (such as a netlist or a set of equations). This training course covers VHDL for PLD synthesis The course will at times draw upon the concepts of VHDL as a simulation language VHDL stands for VHSIC (pronounced “visick”) Hardware Description Language. It is a product of the VHSIC program funded by the DOD (department of defense) in the 70s and 80s. It was mainly developed as a standard means to document circuits designed by DOD contractors. VHDL was established as the IEEE 1076 standard in In 1988, MilStd454 required that all ASICs delivered to the DOD be described in VHDL. In general, you should be familiar with the introduction to the VHDL book.

Why Use VHDL? Quick Time-to-Market
Allows designers to quickly develop designs requiring tens of thousands of logic gates Provides powerful high-level constructs for describing complex logic Supports modular design methodology and multiple levels of hierarchy One language for design and simulation Allows creation of device-independent designs that are portable to multiple vendors. Allows user to pick any synthesis tool, vendor, or device This was basically lifted from Chapter 1 of the book.

PLD Design Flow Design Entry Schematic Capture/HDL or Both
Front-End Simulation (optional) Design Compilation Synthesis, Fitting/Place&Route Design Verification Back-End Simulation (optional) Device Programming There are three main parts of any PLD design, Design Entry Design Compilation Design Verification Section 1.3 of the VHDL book discusses the PLD design flow.

Schematic Text Synthesis Fitting Place&Route Simulation Sim. Model
Design Entry Compilation JEDEC File Prog. Verification Programmer Front End The PLD Design Flow is composed of basically 3 main steps. Design Entry, Design Compilation, and Design Verification. Back End

VHDL Design Descriptions
VHDL design descriptions (referred to as "design entities") consist of an ENTITY declaration and ARCHITECTURE body pair The ENTITY declaration describes the design I/O The ARCHITECTURE body describes the content of the design Emphasize the pairing of entities and architectures. This is the minimum required to synthesize a design.

VHDL Entity/Architecture Pairs: 2-Input And Function
ENTITY and2 IS PORT ( a,b : IN std_logic; f: OUT std_logic); END and2; ARCHITECTURE behavioral OF and2 IS BEGIN f <= a AND b; END behavioral; There should be almost no discussion here. This slide is just an aid for people who learn by example. This is just showing that a design unit is composed of an entity and an architecture.

The Entity A “BLACK BOX”
The ENTITY describes the periphery of the black box (i.e., the design I/O) BLACK_BOX rst q[7:0] d[7:0] co clk

Example Entity declaration
ENTITY black_box IS PORT ( clk, rst: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); q: OUT std_logic_vector(7 DOWNTO 0); co: OUT std_logic); END black_box; More shortly BLACK_BOX rst d[7:0] clk q[7:0] co

The Entity Declaration
ENTITY entity_name IS PORT ( -- optional generics name : mode type ; ... ) ; END entity_name; entity_name is an arbitrary name generics are used for defining paramaterized components name is the signal/port identifier and may be a comma separate list for ports of identical modes and types mode describes the direction the data is flowing type indicates the set of values the port name may be assigned Added by RDC.

Ports The Entity (“BLACK BOX”) has PORTS
PORTS are points of communication PORTS are often associated with the device pins PORTS are a special class of SIGNAL PORTS have an associated SIGNAL name, mode, and type after this foil you can mention that you will now go into detail regarding modes and types

PORT modes A port’s MODE is the direction data is transferred:
IN Data goes into the entity but not out OUT Data goes out of the entity but not in (and is not used internally) INOUT Data is bi-directional (goes into and out of the entity) BUFFER Data that goes out of the entity and is also fed-back internally within the entity You may want to elaborate on BUFFER. Mention that it’s used a lot in counters. Exercise 4 has a good example of this. You may want to draw a picture.

IEEE 1076 Types VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) bit - a signal of type bit that can only take values of '0' or '1' bit_vector - a grouping of bits (each can be '0' or '1') SIGNAL a: BIT_VECTOR(0 TO 3); ascending range SIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0' Mention that bold-faced words in all VHDL code shown in this training indicate VHDL reserved words. You may also want to mention here that VHDL is not case sensitive, e.g. “SIGNAL”, “signal”, and “sIGNaL” all look the same to VHDL. Actually go through the TO and DOWNTO examples and mention that we used DOWNTO most often because most people are accustomed to looking at busses with the MSB on the left. Mention that two dashes indicate the start of a comment. The VHDL analyzer/compiler will ignore everything right of the 2 dashes (to the end of the line) Note how individual bits of a vector are referenced a(0) is read “A sub zero” and references the zeroth bit in the vector.

IEEE 1076 TYPES (contd.) INTEGER
useful as index holders for loops, constants, generics, or high-level modeling BOOLEAN can take values ‘TRUE’ or ‘FALSE’ ENUMERATED has user defined set of possible values, e.g., TYPE states IS (start, slow, fast, stop);

IEEE 1164 "Multi-value logic system for VHDL interoperability"
A package created as an aid to VHDL users Nine values as opposed to two ('0' and '1') Allows increased flexibility in behavioral VHDL coding, synthesis, and simulation std_logic and std_logic_vector are used as opposed to bit and bit_vector when a multi-valued logic system is required. std_logic and std_logic_vector are used when tri-state logic is required. The basic thing to get out of this slide is that std_logic and std_logic_vector are what you should be using.

1164 Types std_logic and std_logic_vector are the industry standard logic type for digital design All 9 values are valid in a VHDL simulator, however only: ‘0’ -- Forcing ‘0’ ‘1’ -- Forcing ‘1’ ‘Z’ -- High Impedance ‘L’ -- Weak ‘0’ ‘H’ -- Weak ‘1’ ‘-’ -- Don’t care are recognized for logic synthesis Warp won’t distinguish between 0 and L (or 1 and H) for PLD synthesis. We take every effort to synthesize code the same way it would simulate. However, not every simulatable construct is synthesizable or representable in hardware. This is where the concept of a synthesizable subset comes in. To address this problem, IEEE is working on defining the synthesizable subset which we will readily adopt. We could have sat that 'U' is the same as '0' or a '-' and an 'X' is the same as a '-', but we did not because we didn't want to create backward compatibility problems once a standard is adopted.

Entity Declaration Example
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY black_box IS PORT ( clk, rst: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); q: OUT std_logic_vector(7 DOWNTO 0); co: OUT std_logic); END black_box; MODE TYPE BLACK_BOX rst d[7:0] clk q[7:0] co Note the library and use statements required to use the 1164 package. Emphasize that not all foils will show these two statements, but you have to have it to use std_logic and std_logic_vector. Read Chapter 3 in the VHDL book for more information.

Exercise #1: The Entity Write an entity declaration for the following:
Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, three-state bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output also used internally Don't let this drag on too long. Just have them scratch the answer on a piece of paper or use notepad or the VHDL editor. We won't synthesize this. There is a template in ex1.vhd if the students want to use the computer. my_design ad[11:0] d[11:0] a[11:0] oe int clk as

Exercise #1: Solution LIBRARY ieee; USE ieee.std_logic_1164.ALL;
ENTITY my_design IS PORT ( d: IN std_logic_vector(11 DOWNTO 0); oe, clk: IN std_logic; ad: INOUT std_logic_vector(11 DOWNTO 0); a: OUT std_logic_vector(11 DOWNTO 0); int: OUT std_logic; as: BUFFER std_logic); END my_design; -- In this presentation, VHDL keywords -- are highlighted in bold, CAPITALS; -- however, VHDL is not case sensitive: -- clock, Clock, CLOCK all refer to the -- same signal, -- means a comment my_design d[11:0] oe clk ad[11:0] a[11:0] int as talk about comments and case insensitivity

The Architecture Architectures describe what is in the black box (i.e., the structure or behavior of entities) Descriptions can be either a combination of Structural descriptions Instantiations (placements of logic-much like in a schematic-and their connections) of building blocks referred to as components Behavioral/Dataflow descriptions Algorithmic (or “high-level”) descriptions: IF a = b THEN state <= state5; Boolean equations (also referred to as dataflow): x <= (a OR b) AND c; More from Chapter 3

The Architecture Declaration
ARCHITECTURE arch_name OF entity_name IS -- optional signal declarations, etc. BEGIN --VHDL statements END arch_name; arch_name is an arbitrary name optional signal declarations are used for signals local to the architecture body (that is, not the entity’s I/O). entity_name is the entity name statements describe the function or contents of the entity Added by RDC.

Architecture Body Styles : Behavioral
ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; ARCHITECTURE behavior OF compare IS BEGIN comp: PROCESS (a,b) IF a = b THEN equals <= '1' ; ELSE equals <= '0' ; END IF ; END PROCESS comp; END behavior; Uses High-Level programming constructs, like in C or Pascal

Architecture Body Styles : Dataflow
ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; ARCHITECTURE dataflow OF compare IS BEGIN equals <= '1' WHEN a = b ELSE '0' ; END dataflow; Uses High-Level programming constructs, like in C or Pascal or rtl/boolean-like descriptions (not algorithms using sequential statements) Sometimes lumped in with behavioral. Obviously not structural.

Architecture Body Styles : Structural
ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; USE WORK.gatespkg.ALL ; ARCHITECTURE structure OF compare IS SIGNAL x : std_logic_vector (0 to 3) ; BEGIN u0: xnor2 PORT MAP (a(0),b(0),x(0)) ; u1: xnor2 PORT MAP (a(1),b(1),x(1)) ; u2: xnor2 PORT MAP (a(2),b(2),x(2)) ; u3: xnor2 PORT MAP (a(3),b(3),x(3)) ; u4: and4 PORT MAP (x(0),x(1),x(2),x(3),equals) ; END structure; more like a netlist gatespkg was created previously

Comparing Architecture Styles
These examples synthesize to equivalent circuits In more elaborate designs, some descriptions may yield more efficient circuits sloppy code = inefficient results (see section 3.3.4) Use styles that make your designs easier to describe and maintain Behavioral/Dataflow exploit module generation (described later) Structural descriptions may make the design less portable (may rely on a library of vendor-specific components) The fact that you can use all these styles is a strength of VHDL. You should point out that some structure is good. For instance if you are doing your own design, creating your own lower-level blocks and connecting them structurally at higher levels is fine. Top-Down/Bottom-Up design techniques work well with VHDL.

Mixing Architecture Styles
The various styles may be mixed in one architecture. ENTITY logic IS PORT ( a,b,c: IN std_logic; f: OUT std_logic); END logic; USE WORK.gatespkg.ALL; ARCHITECTURE archlogic OF logic IS SIGNAL d: std_logic; BEGIN d <= a AND b; g1: nor2 PORT MAP (c, d, f); END archlogic; a b c d f LOGIC g1 This foil is intended to show that you can mix behavioral and structural descriptions in one file. Explain that you won’t get into Port mapping now, but it’s essentially how you wire lower-level components up in a higher level block. You should also elaborate on why a signal is used for “d”. It doesn’t enter or leave the “black box”. You might want to elaborate on the use of signals and variables. I usually say that you can think of a signal as a wire. It can be used to interconnect components. Variables are only used for things like index holders or temporary data storage (and only good in a process). You’ll want to note that signals within architectures are not translated to external pins - only signals within the entity are. Note that signals in architectures do not have a mode because there is no notion of the direction of data flow (into or out of the entity) Behavioral/Dataflow Structural

VHDL Statements There are two types of statements Sequential
Though hardware is concurrent, it may be modeled with algorithms, by a series of sequential statements By definition, sequential statements are grouped using a process statement. Concurrent Statements outside of a process are evaluated concurrently during simulation Processes are concurrent statements the first bullet describing concurrent statements is sort of an oversimplification, but it gets the point across

Concurrent Statements
Concurrent statements include: boolean equations conditional/selective signal assignments (when/else, with/select) instantiations Examples of concurrent statements: -- Examples of boolean equations x <= (a AND (NOT sel1)) OR (b AND sel1); g <= NOT (y AND sel2); -- Examples of conditional assignments y <= d WHEN (sel1 = '1') ELSE c; h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE '1'; -- Examples of instantiation inst: nand2 PORT MAP (h, g, f); Again, you may mention that comments are accomplished using “--”. Everything from the right of the two dashes until the end of the line is ignored by the compiler. You might mention that the WHEN/ELSE statement is a very handy concurrent statement. IF/THEN/ELSE is sequential and must be used within a process. WHEN/ELSE may not be.

The Process Statement Used to construct algorithms/group sequential statements Statements within a process are sequential statements-they execute sequentially during simulation An architecture can contain multiple processes. Each process is executed concurrently Processes may be used to model combinational or synchronous logic Even though hardware is operates "concurrently" you can model it by a series of sequential statements. Refer to Section 3.3 of the book for more info.

The Process (contd.) label: PROCESS (sensitivity list)
-- variable declarations BEGIN -- sequential statements END PROCESS label ; The process label and variable declarations are optional The process executes when one of the signals in the sensitivity list has an event (changes value). Discuss the template for a process.

Process (contd.) Processes are executing or suspended (active or inactive/awake or asleep) A process typically has a sensitivity list When a signal in the sensitivity list changes value, the process is executed by the simulator e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal All signal assignments occur at the END PROCESS statement in terms of simulation The process is then suspended until there is an event (change in value) on a signal in the sensitivity list Mention that you will explain why the comment about signal assignments occurring at the END PROCESS statement is so important.

Combinational Logic Can be described with concurrent statements
e.g. with-select-when, when-else, boolean equations, component instantiatons Can be described with sequential statements e.g. if-then-else, case-when

Combinational Logic w/ Boolean Equations
Boolean Equations can be used in both concurrent and sequential signal assignment statements. A 4-1 multiplexer is shown below x <= (a AND NOT(s(1)) AND NOT(s(0))) OR (b AND NOT(s(1)) AND s(0)) OR (c AND s(1) AND NOT(s(0))) OR (d AND s(1) AND s(0)) ; s 2 a The NOT operator has higher precedence than any of the other boolean operators. The rest are (and, nand, xor, etc.) are of equal precedence so you just used parentheses where necessary. b x mux c d

Selective Signal Assignment: with-select-when
Assignment based on a selection signal WHEN clauses must be mutually exclusive Use a WHEN OTHERS to avoid latches Only one reference to the signal, only one assignment operator (<=) WITH selection_signal SELECT signal_name <= value_1 WHEN value_1 of selection_signal, value_2 WHEN value_2 of selection_signal, ... value_n WHEN value_n of selection_signal, value_x WHEN OTHERS;

Combinational Logic w/ Selective Signal Assignment
The same 4-1 multiplexer is shown below with s select x <= a when “00” , b when “01” , c when “10” , d when others ;

More on with-select-when
You can use a range of values with int_value select x <= a when 0 to 3, b when 4 | 6 | 8 , c when 10 , d when others ;

Conditional Signal Assignment: when-else
Signal is assigned a value based on conditions Any simple expression can be a condition Priority goes in order of appearance Only one reference to the signal, only one assignment operator (<=) Use a final ELSE to avoid latches signal_name <= value_1 WHEN condition1 ELSE value_2 WHEN condition2 ELSE ... value_n WHEN conditionn ELSE value_x ;

Combinational Logic w/ Conditional Signal Assignment
The same 4-1 multiplexer is shown below x <= a when (s = “00”) else b when (s = “01”) else c when (s = “10”) else d ;

Combinational Logic w/ Conditional Signal Assignment
The when conditions do not have to be mutually exclusive (as in with-select-when) A priority encoder is shown below j <= w when (a = ‘1’) else x when (b = ‘1’) else y when (c = ‘1’) else z when (d = ‘1’) else ‘0’ ; The schematic is shown on page 169 of the book. The equation for j is as folows j = a * w + /a * b * x + /a * /b * c * y + /a * /b * /c * d * z so you can see the first condition in the when/else has priority. If a is high, j gets w, no matter what b, c, and d are equal to, but if a is low, then j gets x if b is high, independent of c and d. You could explicitly use boolean equations if you did not want/need priority, eg. j <= (a AND w) or (b AND x) or (c AND y) or (d AND z)

Combinational Logic w/ Sequential Statements
Grouped together with Processes Processes are concurrent with one another and with concurrent statements Order of sequential statements does make a difference in synthesis

Sequential Statements if-then-else
Used to select a set of statements to be executed Selection based on a boolean evaluation of a condition or set of conditions IF condition(s) THEN do something; ELSIF condition_2 THEN -- optional do something different; ELSE optional do something completely different; END IF ;

if-then-else Absence of ELSE results in implicit memory
4-1 mux shown below mux4_1: process (a, b, c, d, s) begin if s = “00” then x <= a ; elsif s = “01” then x <= b ; elsif s = “10” then x <= c ; else x <= d ; end process mux4_1 ;

Sequentional Statements: Case-When
CASE selection_signal WHEN value_1_of_selection_signal => (do something) -- set of statements 1 WHEN value_2_of_selection_signal => (do something) -- set of statements 2 ... WHEN value_N_of_selection_signal => (do something) -- set of statements N WHEN OTHERS => (do something) -- default action END CASE ; Case-when statements are used to specify a set of statements to execute based on the value of a given selection siganal (sort of the sequential counterpart to the with-select-when).

The CASE Statement: 4-1 Mux
ARCHITECTURE archdesign OF design IS SIGNAL s: std_logic_vector(0 TO 1); BEGIN mux4_1: PROCESS (a,b,c,d,s) CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10” => x <= c; WHEN OTHERS => x <= d; END CASE; END PROCESS mux4_1; END archdesign; You may want to mention that multiple statements can be executed for each case value.

Sequential Statements: An Example
mux: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mux; x(3 DOWNTO 0) s a(3 DOWNTO 0) b(3 DOWNTO 0) Note: logic within a process can be registered or combinatorial Note: the order of the signals in the sensitivity list is not important Note: the process mux is sensitive to signals a, b, and s; i.e., whenever one or more of those signals changes value, the statements inside of the process are executed

Signal Assignment in Processes Which Circuit is Correct?
BEGIN WAIT UNTIL clock = '1' ; -- implied sensitivity list b <= a; c <= b; END PROCESS ; signals c an b are scheduled You may want to mention that most synthesis tools only allow wait statements to be the first or last line of the process, whereas simulators allow it anywhere. Warp requires it to be the first line. a b c c a clock clock

Signal Assignment in Processes (contd.)
Signals are not updated immediately. Rather, they are scheduled. The signals are not updated until time advances (after the End Process statement) Therefore, two registers will be synthesized Note: In some instances, the use of concurrent statements outside the process may alleviate the problem, but this is not possible with registered logic.

VARIABLES When a concurrent signal assignment cannot be used, the previous problem can be avoided using a VARIABLE Variables can only exist within a PROCESS, they cannot be used to communicate information between processes Variables can be of any valid data type The value assigned to a variable is available immediately The variable assignment statement is used to assign values to variables, e.g., c := a AND b;

Using Variables vs. Signals
Solution using a variable within a process: -- assume a and c are signals defined elsewhere PROCESS VARIABLE b : std_logic ; BEGIN WAIT UNTIL clock = '1' ; b := a ; -- this is immediate c <= b ; -- this is scheduled END PROCESS ;

Native Operators Logical - defined for type bit, bit_vector, boolean*
AND, NAND OR, NOR XOR, XNOR NOT Relational - defined for types bit, bit_vector, integer* = (equal to) /= (not equal to) < (less than) <= (less than or equal to) > (greater than) >= (greater than or equal to) * overloaded for std_logic, std_logic_vector The NOT operator has higher precedence than any of the other boolean operators. The rest are (and, nand, xor, etc.) are of equal precedence so you just used parentheses where necessary. Relational operators return a boolean value. When companring vectors of different lengths, the comparison is done from left to right. Therefore "111" is greater than "10111".

Native Operators (contd.)
Unary Arithmetic - defined for type integer* - (arithmetic negate) Arithmetic - defined for type integer* + (addition), * (multiplication) - (subtraction) Concatenation - defined for strings & Note, a STRING is any sequence of characters, therefore a std_logic_vector is an example of a STRING * overloaded for std_logic, std_logic_vector We do only unsigned arithmetic now. This may change in release 5.0 (may be some additional capability in 4.2). Mention that we will use the concatenation operator when fixing the pinout of a device for purposes of code readability. It can also be used to concatenate vectors. This is not a complete set of operators. Other operators include /, mod, rem, abs, ** Warp supports abs and ** (for powers of 2 anyway), but not /, mod, or rem.

Overloaded Operators In VHDL, the scope of all of the previous operators can be extended (or overloaded) to accept any type supported by the language, e.g., -- assume a declaration of a 16-bit vector as SIGNAL pc IS std_logic_vector(15 DOWNTO 0); -- then a valid signal assignment is pc <= pc + 3; -- assuming the '+' operator has been overloaded to --- accept std_logic_vector and integer operands The std_logic_1164 package defines overloaded logical operators (AND, OR, NOT, etc.,) for the std_logic and std_logic_vector types In this training, you will learn to use overloaded operators, but not to define them This concept is also used in C++ and other Object-Oriented programming languages.

Using Tri-State Logic ENTITY test_three IS PORT( oe : in std_logic;
data : out std_logic_vector(0 to 7)); END test_three; ARCHITECTURE archtest_three OF test_three IS BEGIN PROCESS (oe) IF (oe = '1') THEN data <= " "; ELSE data <= "ZZZZZZZZ"; END IF; END PROCESS; END archtest_three; Warp will utilize the tri-state buffer in the part when you write code like this.

Behavioral Don’t Cares
Can use explicit "don’t care" conditions to produce optimal logic equations IF (a = '1') AND (b = '1') THEN x <= c; ELSE x <= '-'; END IF; Produces the equation x = c To assign don’t cares in VHDL: mysig <= '-'; 'X' means "unknown" and is not useful for synthesis std_match must be used when doing any comparison of vectors containing don't cares.

Comparing Vectors to Strings -more on don't cares-
Comparing "1101" to "11-1" will return FALSE Use std_match(a,"string") Must include std_arith package Example: ... signal a : stdlogic_vector (1 to 4) ; IF (std_match(a,"10-1")) THEN x <= '1' ; END IF ; page 124 of the Warp release 4.0 reference manual std_match is defined in IEEE the original package may be found in lib/prim/presynth

Legal VHDL Identifiers
Letters, digits, and underscores only (first character must be a letter) The last character cannot be an underscore Two underscores in succession are not allowed Using reserved words is not allowed Examples Legal tx_clk, Three_State_Enable, sel7D, HIT_1124 Not Legal _tx_clk, 8B10B, large#num, register, clk_ Appendix B in the VHDL book has a list of reserved words.

Exercise #2: Architecture Declaration of a Comparator
The entity declaration is as follows: aeqb a(0 TO 3) b(0 TO 3) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); aeqb: OUT std_logic); END compare; 10-15 minutes is plenty long for this exercise Have them use the template found in ex2.vhd. Those that are faster can go ahead and play with warp if they are adventurous. Write an architecture that causes aeqb to be asserted when a is equal to b Multiple solutions exist

Three possible solutions
Concurrent statement solution using a conditional assignment: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= '1' WHEN a = b ELSE '0'; END archcompare; Concurrent statement solution using boolean equations: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= NOT( (a(0) XOR b(0)) OR (a(1) XOR b(1)) OR (a(2) XOR b(2)) OR (a(3) XOR b(3))); END archcompare;

Three possible solutions (contd.)
Solution using a process with sequential statements: ARCHITECTURE archcompare OF compare IS BEGIN comp: PROCESS (a, b) IF a = b THEN aeqb <= '1'; ELSE aeqb <= '0'; END IF; END PROCESS comp; END archcompare; aeqb a(0 TO 3) b(0 TO 3)

Exercise #3: The Schematic
en(1) en(2) en(3) en[0:3] dir en(0) gnd CY74FCT373T CY74FCT245T PLD addr[1:0] nvalid nOE LE data[7:0] status[7:0] control[7:0] T/R Basically we are using a PLD to control the operation of the other parts (which are 8-bit latches).

Exercise #3 Use Warp to compile the VHDL design description of the truth table below: addr nvalid b"00" '0' '1' b"01" b"10" b"11" dir L H en(0) en(1) en(2) en(3) I usually give a big hint here and mention that this can be done with 5 WHEN/ELSE statements. Use the template given in ex3.vhd. Write the Architecture for the given Entity (next) Save design in file named “ex3.vhd”

Exercise #3: The Entity Declaration
the entity declaration is as follows: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex3 IS PORT ( addr: IN std_logic_vector(1 DOWNTO 0); nvalid: IN std_logic; en: BUFFER std_logic_vector(0 TO 3); dir: OUT std_logic ); END ex3; en dir addr nvalid PLD

Exercise #3: Solution The Architecture
The architecture is as follows: ARCHITECTURE archex3 OF ex3 IS BEGIN en(0) <= '0' WHEN (addr = "00" AND nvalid = '0') ELSE '1'; en(1) <= (NOT addr(1)) AND addr(0) AND (NOT nvalid) ; en(2) <= '0' WHEN (addr = "10" AND nvalid = '0') ELSE '1'; en(3) <= addr(1) AND addr(0) AND (NOT nvalid); dir <= '0' WHEN (addr = "00" AND nvalid = '0') OR (addr = "10" AND nvalid = '0') ELSE '1' ; END archex3; If someone looks ahead and uses a case statement, they need to make sure and use a when others. Also remember that since the type is std_logic, there may be many uncovered cases (not just 2 to the power of the number of bits). Also people may try to use don't cares. You have to use std_match for don't care comparison.

Aggregates and Subscripts
Aggregate assignment concatenates signals together Good for creating a bus from several inputs Concatenation operator can be used as well Same number of array elements on both sides of <= tmp <= (a,b,c,d); tmp <= a & b & c & d; Signals can be “pulled” from larger vectors Good for grouping outputs as an “alias” Sizes on both sides must match rw <= ctrl(0); ce <= ctrl(1); oe <= ctrl(2); highcount <= count(7 DOWNTO 4);

Exercise #3: Alternate Solution
Using With/Select and aggregates ARCHITECTURE archex3 OF ex3 IS SIGNAL control : std_logic_vector(2 DOWNTO 0); SIGNAL outputs : std_logic_vector(0 TO 4); BEGIN control <= addr & nvalid; WITH control SELECT outputs <= "00100" WHEN "000", "10101" WHEN "001", "11101" WHEN "010", "10101" WHEN "011", "10000" WHEN "100", "10101" WHEN "101", "10111" WHEN "110", "10101" WHEN "111", "-----" WHEN OTHERS; en <= outputs(0 TO 3); dir <= outputs(4); END archex3;

Designs that use Registers
There are two methods of utilizing and generating flip-flops: Instantiate (place) a flip-flop or a component that contains a flip-flop Use a process that is sensitive to a clock edge

Instantiating a registered component
Example: Using LPM library LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE WORK.lpmpkg.all ; ENTITY registered IS PORT ( d, clk: IN std_logic; q: OUT std_logic); END registered; ARCHITECTURE archregistered OF registered IS BEGIN flipflop: Mff generic map (lpm_width=>1,lpm_fftyp=>lpm_dff) PORT MAP (data=>d,clock=>clk,enable=>one,q=>q); END archregistered; q d clk When describing the USE statement in this case, You may want to point out that sometimes you may want to instantiate a specific component from a library. This is useful for documentation purposes or if you are using two libraries with identical component names. It is not recommended that you use the LPM library in Warp2, but it's there for people that are used to using gates. The graphical LPM interface in Warp3 is very nice.

Registers in Behavioral VHDL
Example: a D-type flip-flop ENTITY registered IS PORT ( d, clk: IN std_logic; q: OUT std_logic); END registered; ARCHITECTURE archregistered OF registered IS BEGIN flipflop: PROCESS (clk) IF clk’EVENT AND clk = '1' THEN q <= d; END IF; END PROCESS flipflop; END archregistered;

Registers in Behavioral VHDL
The synthesis compiler infers that a register is to be created for which signal q is the output because The clock (clk) is in the sensitivity list The construct, clk’event and clk = ‘1’, appears in the process The clk’event and clk = ‘1’ statement implies that subsequent signal assignments occur on the rising-edge of the clock The absence of an “else” clause in the “if-then” statement implies that if the clk’event and clk = ‘1’ condition is not fulfilled (i.e. not a rising-edge), q will retain its value until the next assignment occurs (this is referred to as implied memory)

A Registered Process (1)
A 4-bit counter with synchronous reset USE WORK.std_arith.ALL; ... upcount: PROCESS (clk) BEGIN IF clk’EVENT AND clk= '1' THEN IF reset = '1' THEN count <= "0000"; -- or x"0" instead ELSE count <= count + 1; END IF; END PROCESS upcount; If it hasn’t been mentioned already, you should point out that the std_arith package allows you to add an integer to a std_logic_vector. You can ask the class if they can make a guess at how to make this design have an asynchronous reset. mention that this is just a code fragment that would have to be enclosed in an architecture which is paired with an entity. This process is only sensitive to changes in “clk”, i.e., it will become active only when the clock transitions

A 4-bit counter with asynchronous reset USE WORK.std_arith.ALL; ... upcount: PROCESS (clk, rst) BEGIN IF rst = '1' THEN count <= x"0"; ELSIF clk’EVENT AND clk = '1' THEN count <= count + 1; END IF; END PROCESS upcount; This process is sensitive to changes in both clk and rst, i.e., it will become active during clock or reset transitions.

A 4-bit loadable counter with asynchronous reset USE WORK.std_arith.ALL; ... upcount: PROCESS (clk, rst) BEGIN IF rst = '1' THEN count <= x"0" ; ELSIF clk’EVENT AND clk = '1' THEN IF load = '1' THEN count <= data; ELSE count <= count + 1; END IF; END PROCESS upcount;

The WAIT statement This is another method to activate a process
The WAIT statement is a sequential statement which suspends the execution of a process until the condition specified becomes valid (true) i.e., an implied sensitivity list, e.g., sync: PROCESS BEGIN WAIT UNTIL clock='1'; IF enable='1' THEN q_out <= d_in; ELSE q_out <= '0'; END IF; END PROCESS sync; D enable d_in clock Q q_out Go quickly through this foil. We mentioned the wait statement already. The wait statement must be the first statement in the process. (the compiler will complain if this is not the case) This does implement edge-triggered circuitry even though it may look like it should implement level-triggered to some folks.

Implicit memory Signals in VHDL have a current value and may be scheduled for a future value If the future value of a signal cannot be determined, a latch will be synthesized to preserve its current value Advantages: Simplifies the creation of memory in logic design Disadvantages: Can generate unwanted latches, e.g., when all of the options in a conditional sequential statement are not specified The statement “simplifies creation of memory in a design” ... for example if (clk’event and clk = ‘1’) then q <= d ; end if; you don’t have to add else q <= q

Implicit memory: Example of incomplete specification
ARCHITECTURE archincomplete OF incomplete IS BEGIN im_mem: PROCESS (a,b) IF a = '1' THEN c <= b; END IF; END PROCESS im_mem; END archincomplete; a c b The user wants a simple AND gate, but gets all that extra logic. Note: the incomplete specification of the IF...THEN... statement causes a latch to be synthesized to store the previous state of ‘c’

Example of complete specification
Implicit memory: Example of complete specification ARCHITECTURE archcomplete OF complete IS BEGIN no_mem: PROCESS (a, b) IF a = '1' THEN c <= b; ELSE c <= '0'; END IF; END PROCESS no_mem; END archcomplete; b c a The conditional statement is fully specified, and this causes the process to synthesize to a single gate

The rules to avoid implicit memory
To avoid the generation of unexpected latches always terminate an IF...THEN... statement with an ELSE clause cover all alternatives in a CASE statement define every alternative individually, or terminate the CASE statement with a WHEN OTHERS... clause, e.g., CASE select IS WHEN b"100" => key <= first; x <= a AND b; WHEN b"010" => key <= second; WHEN b"001" => key <= third; WHEN OTHERS => key <= none; END CASE; Warp will actually give you an error if you don't use a WHEN OTHERS and haven't specified all the cases.

Exercise #4 Making use of the previous examples, write an entity/architecture pair for the following design: ENC COUNTER DATA DIN LD 4 COUNT LD Q 4 ENC COMPARATOR CLOCK use ex4.vhd as a template I made the template not quite so easy as ex3 so the basic syntax would become more familiar. P RST RESET (sync) P=Q Q REGISTER DIN Q ENR 4 ENR

ENTITY ex4 IS PORT ( clock, reset, enc, enr, ld: IN std_logic; data: IN std_logic_vector (3 DOWNTO 0); count: BUFFER std_logic_vector(3 DOWNTO 0)); END ex4; USE WORK.std_arith.ALL; -- for counter and ultragen ARCHITECTURE archex4 OF ex4 IS SIGNAL comp: std_logic; SIGNAL regout: std_logic_vector (3 DOWNTO 0); BEGIN reg: PROCESS (clock) IF clock'EVENT AND clock = '1' THEN IF enr = '1' THEN regout <= data; END IF; END PROCESS reg;

Exercise #4: Solution (contd.)
cntr: PROCESS (clock) BEGIN IF clock'EVENT AND clock = '1' THEN IF reset = '1' THEN count <= "0000"; ELSIF ld = '1' THEN count <= data; ELSIF enc = '1' AND comp = '0' THEN count <= count + 1; END IF; END PROCESS cntr; comp <= '1' WHEN regout = count ELSE '0'; END archex4;

State machines Moore Machines
A finite state machine in which the outputs change due to a change of state Mealy Machines A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately Review Chapter 5 in the VHDL Book

Moore machines Outputs may change only with a change of state
Multiple implementations include: Arbitrary state assignment outputs must be decoded from the state bits combinatorial decode registered decode Specific state assignment outputs may be encoded within the state bits one-hot encoding

Moore state machine implementations (1)
Outputs decoded from state bits Combinatorial decode Outputs are decoded combinatorially from the current state outputscomb = f(present state) State Registers Output Logic Outputs Logic Inputs

Moore state machine implementations (2)
Outputs decoded from state bits Registered decode Outputs are registered; decode of outputs is in parallel with decode of next state outputsreg = f(previous state, inputs) Current State Next State Logic State Registers Inputs Output Logic Output Registers Outputs

Moore State Machine Implementations (3)
Outputs encoded within state bits Example: State Output 1 Output 2 State Encoding s1 00 s2 1 01 s3 1 10 Note: Both bits of the state encoding are used as outputs State Registers Outputs Logic Inputs

Example: A wait state generator
State diagram: PWAIT RESET (async) ack_out='1' IDLE REQ RETRY PWAIT ACK 00 01 10 REQ retry_out='1'

Example: The entity declaration
The entity declaration remains essentially the same for each implementation (except for the entity name) e.g., LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY moore1 IS PORT ( clock, reset: IN std_logic; req, pwait: IN std_logic; retry_out, ack_out: OUT std_logic); END moore1;

Example: Solution 1 Combinatorial outputs decoded from the state bits
ARCHITECTURE archmoore1 OF moore1 IS TYPE fsm_states IS (idle, retry, ack); SIGNAL wait_gen : fsm_states; BEGIN fsm: PROCESS (clock, reset) IF reset = '1' THEN wait_gen <= idle; -- asynchronous reset ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF; WHEN retry => IF pwait='1' THEN wait_gen <= ack; ELSE wait_gen <= retry;

Example: Solution 1 (contd.)
WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END IF; END PROCESS fsm; retry_out <= '1' WHEN (wait_gen = retry) ELSE '0'; ack_out <= '1' WHEN (wait_gen = ack) ELSE '0'; END archmoore1;

Example: Solution 2 Registered outputs decoded from the state bits
ARCHITECTURE archmoore2 OF moore2 IS TYPE fsm_states IS (idle, retry, ack); SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) IF reset = '1' THEN wait_gen <= idle; retry_out <= '0'; ack_out <= '0'; ELSIF clock'EVENT AND clock = '1' THEN retry_out <= '0'; -- a default assignment, could do ack_out too CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; retry_out <= '1'; ELSE wait_gen <= idle; END IF; some designers like to initialize their signals like shown with retry_out some like to assign the values specifically this example shows as mixture of the two.

WHEN retry => IF pwait = '1' THEN wait_gen <= ack; ack_out <= '1'; ELSE wait_gen <= retry; retry_out <= '1'; ack_out <= '0'; END IF; WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; ack_out <= '0'; -- note must define what -- happens to ‘ack_out’ END CASE; -- here or a latch will END IF; -- be synthesized to END PROCESS fsm; -- preserve it’s current END archmoore2; -- state

Example: Solution 3 Outputs encoded within the state bits
ARCHITECTURE archmoore3 OF moore3 IS SIGNAL wait_gen: std_logic_vector(1 DOWNTO 0); CONSTANT idle: std_logic_vector(1 DOWNTO 0) := "00"; CONSTANT retry: std_logic_vector(1 DOWNTO 0) := "01"; CONSTANT ack: std_logic_vector(1 DOWNTO 0) := "10"; BEGIN fsm: PROCESS (clock, reset) IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF;

WHEN retry => IF pwait = '1' THEN wait_gen <= ack; ELSE wait_gen <= retry; END IF; WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END PROCESS fsm; retry_out <= wait_gen(0); ack_out <= wait_gen(1); END archmoore3;

State Machines: One-hot Encoding
One state per flip-flop in FPGA-type architectures reduces the next state logic requires fewer levels of logic cells enables high-speed state machines (> 100MHz) in CPLDs reduces the number of product terms can eliminate ‘expander’ product terms (i.e. reduce delays, and increase operating speed) but, uses more macrocells

Example: One-hot-one Solution
ARCHITECTURE archmoore4 OF moore4 IS TYPE fsm_states IS (idle, retry, ack); ATTRIBUTE state_encoding OF fsm_states:TYPE IS one_hot_one; SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF;

Example: One-hot-one Solution (contd.)
WHEN retry => IF pwait = '1' THEN wait_gen <= ack; ELSE wait_gen <= retry; END IF; WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END PROCESS fsm; -- Assign state outputs retry_out <= '1' WHEN (wait_gen = retry) ELSE '0'; ack_out <= '1' WHEN (wait_gen = ack) ELSE '0'; END archmoore4;

Moore Machines: Summary
Outputs decoded from the state bits flexibility during the design process using enumerated types allows automatic state assignment during compilation Outputs encoded within the state bits manual state assignment using constants the state registers and the outputs are merged reduces the number of registers but, may require more product terms One-Hot encoding reduces next state decode logic high speed operation but, uses more registers

Mealy Machines Outputs may change with a change of state OR with a change of inputs Mealy outputs are non-registered because they are functions of the present inputs State Registers Outputs Logic Inputs

Example: The Wait State Generator
State diagram: PWAIT RESET (async) IDLE REQ RETRY RETRY_OUT='1' 1 if, ENABLE='0' REQ PWAIT

Example: Mealy Machine Solution
ARCHITECTURE archmealy1 OF mealy1 IS TYPE fsm_states IS (idle, retry); SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF; WHEN retry => IF pwait = '1' THEN wait_gen <= idle; ELSE wait_gen <= retry; WHEN OTHERS => wait_gen <= idle; END CASE; END PROCESS fsm; retry_out <= '1' WHEN (wait_gen = retry AND enable='0') ELSE '0'; END archmealy1;

Exercise #5 Design a state machine to implement the function shown below: RESET POS hold sample extend use the template in ex5.vhd POS clear='0' track='1' if, busy='0' track='1' RESET

ENTITY ex5 IS PORT ( clock, pos, busy, reset: IN std_logic; clear, track: OUT std_logic); END ex5; ARCHITECTURE archex5 OF ex5 IS TYPE states IS (hold, sample, extend); ATTRIBUTE state_encoding OF states:TYPE IS one_hot_one; SIGNAL fsm: states; BEGIN clear <= '0' WHEN fsm = sample ELSE '1'; track <= '1' WHEN (fsm = sample) OR (fsm = extend AND busy = '0') ELSE '0';

sync: PROCESS (clock) BEGIN IF clock'EVENT AND clock = '1' THEN IF reset = '1' THEN fsm <= hold; -- synchronous reset ELSE CASE fsm IS WHEN hold => IF pos = '0' THEN fsm <= sample; ELSE fsm <= hold; END IF; WHEN sample => fsm <= extend; WHEN extend => fsm <= hold; WHEN OTHERS => fsm <= hold; END CASE; END IF; -- reset = '1' END IF; -- clk'EVENT AND clk = '1' END PROCESS sync; END archex5;

Hierarchical design methodology
Advantages: Allows the re-use of common building blocks Components (VHDL models or schematic symbols) can be created, tested and held for later use Smaller components can be more easily integrated with other blocks Designs are more readable Designs are more portable The design task can be split among several members of a team

Hierarchy decomposition
A VHDL hierarchy is composed of COMPONENTs declarations of VHDL models which can be instantiated (placed) within other models PACKAGEs a collection of one or more COMPONENT (and other) declarations

Packages and hierarchical designs
Packages contain components, types, and/or subtypes which can be used in other designs Components are entity/architecture pairs with component declarations Designs that make use of components or types in packages must include a USE clause, e.g., USE WORK.my_package.ALL; The above allows the VHDL code to instantiate all components/types in my_package USE WORK.my_package.cnt4; The above allows the VHDL code to instantiate only the cnt4 components in my_package

Packages: How it all fits together
b sel mux2to1 a c r toplevel q s c b mux2to1 a sel i t p schematic entity/architecture schematic entity/architecture c b mux2to1 a sel The top bullets are for schematic design - the bottom for VHDL In schematic capture, you connect lower level logic gates together. In VHDL you use an entity/architecture pair. In schematic design, you create a symbol out of your lower-level design. In VHDL, you make a component In schematic design, your group of symbols goes into a schematic library. In VHDL, your components go in a package. In schematic design, you pull symbols from your library and place (instantiate) them in your top-level schematic. In VHDL, you place (instantiate) components from a package into your top-level entity/architecture. library package symbol component

Package declaration: Example
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mux2to1 IS PORT ( a, b, sel: IN std_logic; -- port list c: OUT std_logic); END mux2to1; ARCHITECTURE archmux2to1 OF mux2to1 IS BEGIN c <= (a AND NOT sel) OR (b AND sel); END archmux2to1; LIBRARY ieee; -- note repeated LIBRARY USE ieee.std_logic_1164.ALL; -- and USE statements PACKAGE mymuxpkg IS COMPONENT mux2to1 PORT ( a, b, sel: IN std_logic; -- identical port list END COMPONENT; END mymuxpkg;

Hierarchical design: Example
Signals are connected via a PORT MAP that associates signals with the component's I/O Port map association can be either explicit (named) or implicit (positional) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY toplevel IS PORT (s: IN std_logic; p, q, r: IN std_logic_vector(2 DOWNTO 0); t: OUT std_logic_vector(2 DOWNTO 0)); END toplevel; USE WORK.mymuxpkg.ALL; ARCHITECTURE archtoplevel OF toplevel IS SIGNAL i: std_logic_vector(2 DOWNTO 0); BEGIN m0: mux2to1 PORT MAP (a=>i(2), b=>r(0), sel=>s, c=>t(0)); m1: mux2to1 PORT MAP (c=>t(1), b=>r(1), a=>i(1), sel=>s); m2: mux2to1 PORT MAP (i(0), r(2), s, t(2)); i <= p AND NOT q; END archtoplevel; Named Association Positional Association

Exercise #6: The Design OE DECODER MUX DATA LOAD UPCNT ENABLE CLOCK
8 DECODER 8 MUX 8 DATA 8 LOAD 4 (LSB) UPCNT ENABLE The MSB and LSB of the upcounter each drive 7-segment LED displays (with a period). The decoders determine which LEDs to turn on to get the appropriate number displayed. The counter is loadable with an asynchronous reset. The data inputs, through the use of multiplexers, can also directly drive the LEDs (of course they don't go through the decoder so the display may be nonsense). The outputs of the mux can be disabled through the use of tri-state buffers. The students should be given all templates except for the package for the upcounter, which they should write. This design is mainly to illustrate the use of hierarchy in VHDL. The fast finishers can simulate the design. There are two new timings in the report file. tro - asynchronous reset to output and ter - input to output disable 4 (MSB) CLOCK DECODER DECODER 8 MUX RESET 8 TEST

Exercise #6 Write a hierarchical VHDL description of the previous schematic which instantiates all of the components shown in the design entity/architecture given for top-level design package/entity/architecture given for decoder entity/architecture given for counter, write package The target device is a CY7C371I-143JC Compile and synthesize your design using Warp Get the following files in the project dcodepkg.vhd decoder.vhd upcnt.vhd upcntpkg.vhd ex6.vhd upcntpkg.vhd is the only one that has to be edited. ex6.vhd is the top-level file. The students should review all the files.

Exercise #6: dcodepkg.vhd
Analogous to mymuxpkg A entity/architecture for a 7-segment display decoder is provided in the file - ’decoder.vhd’ A package declaration is also provided in the file - ‘dcodepkg.vhd’, e.g.: LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE dcodepkg IS COMPONENT decoder PORT( digit: IN std_logic_vector(3 DOWNTO 0); leds: OUT std_logic_vector(7 DOWNTO 0)); END COMPONENT; END dcodepkg;

Exercise #6: upcnt.vhd Analogous to mux2to1 and archmux2to1
An entity/architecture pair for an 8-bit loadable counter is provided in the file - ‘upcnt.vhd’ In a separate file create a package declaration for the counter based on the entity in upcnt.vhd: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY upcnt IS PORT ( clock, load, reset, enable: IN std_logic; data: IN std_logic_vector(7 DOWNTO 0); count: OUT std_logic_vector(7 DOWNTO 0)); END upcnt;

Exercise #6 top level: - ex6.vhd
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex6 IS PORT( clock, load, enable, test, oe, reset: IN std_logic; data: IN std_logic_vector(7 DOWNTO 0); seg7hi, seg7lo: OUT std_logic_vector(7 DOWNTO 0)); END ex6; USE WORK.upcntpkg.ALL; USE WORK.dcodepkg.ALL; ARCHITECTURE archex6 OF ex6 IS SIGNAL hicode, locode, count: std_logic_vector(7 DOWNTO 0); BEGIN c1: upcnt PORT MAP (clock, load, reset, enable, data, count); d1: decoder PORT MAP (count(7 DOWNTO 4), hicode); d2: decoder PORT MAP (count(3 DOWNTO 0), locode); seg7hi <= "ZZZZZZZZ" WHEN oe = '0' ELSE hicode WHEN test = '0' ELSE data; seg7lo <= (OTHERS => 'Z') WHEN oe = '0' ELSE locode WHEN test = '0' ELSE data; END archex6; Note the nested WHEN/ELSE and the behavioral implementation of the tri-state buffer in the WHEN/ELSE.

Exercise #6: Instructions
Write package for the upcounter Add all of the necessary files to the input list, the top-level file (ex6.vhd) should be last Click-on the Device button to select the target device Highlight the top-level file and Click-on the Set top button in the Compiler options Except for the file containing the top-level, highlight each file in turn and Click-on Selected in the Compile box Finally, highlight and then compile the top-level file to synthesize the design. Smart will compile only files that have been updated since the last compile.

Exercise #6: Solution - upcntpkg.vhd
LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE upcntpkg IS COMPONENT upcnt PORT( clock, load, reset, enable: IN std_logic; data: IN std_logic_vector(7 DOWNTO 0); count: OUT std_logic_vector(7 DOWNTO 0)); END COMPONENT; END upcntpkg;

Creating repetitive structures
e.g., a 32-bit serial to parallel converter: reset si clock q(31) q(30) q(29) q(1) q(0) • • • It helps to draw this as the VHDL in the next foil goes through the values of i po(31) po(30) po(29) po(1) po(0)

The GENERATE statement
Used to specify repetitive or conditional execution of a set of concurrent statements Useful for instantiating arrays of components ENTITY sipo IS PORT ( clk, reset: IN std_logic; si: IN std_logic; po: BUFFER std_logic_vector(31 DOWNTO 0)); END sipo; USE WORK.rtlpkg.ALL; -- User-defined package containing dsrff ARCHITECTURE archsipo OF sipo IS BEGIN gen: FOR i IN 0 TO 30 GENERATE nxt: dsrff PORT MAP (po(i+1), zero, reset, clk, po(i)); END GENERATE; beg: dsrff PORT MAP (si, zero, reset, clk, po(31)); END archsipo;

Multiplexing I/O pins:
LIBRARY ieee ; USE ieee.std_logic_1164.ALL; USE WORK.std_arith.all ; ENTITY ldcnt IS PORT ( clk, ld, oe: IN std_logic; count: INOUT std_logic_vector(7 DOWNTO 0)); END ldcnt; ARCHITECTURE archldcnt OF ldcnt IS SIGNAL int_count: std_logic_vector(7 DOWNTO 0); BEGIN cnt: PROCESS (clk) IF clk’EVENT AND clk = '1' THEN IF ld = '1' THEN int_count <= count; -- count as "IN" ELSE int_count <= int_count + 1; END IF; END PROCESS cnt ; outen: PROCESS (oe, int_count) BEGIN IF oe = '1' THEN count <= int_count ; -- count as "OUT" ELSE count <= (OTHERS => 'Z') ; -- count as "OUT" END IF ; equivalent to count <= "ZZZZZZZZ" END PROCESS outen; END archldcnt; The count <= (OTHERS => 'Z') ; statement simply sets all the bits of "count" to 'Z'. Believe it or not, the case of the Z is important here. I don't know why. I believe it is because case matters in enumerated types. This re-enforces an earlier slide so don't spend too much time on it.

Exercise #7 Design a Moore Machine to implement the Output Enable Controller shown below: 68040 DRAM BANK A DRAM BANK B Don't bother doing this exercise. DRAM BANK C DRAM BANK D Output DRAM Enable Controller Controller

Exercise #7: The FSM chart
Use the following FSM chart: We usually don't get to this example and leave it as an exercise to the student. The solution is of a style different than those previously shown and looks more like what is in the VHDL book. The outputs are decoded in parallel with the next state so they are available in tco instead of tco2.

Exercise #7: Solution ENTITY ex7 IS PORT ( clk, reset: IN std_logic;
ram, eoc: IN std_logic; a3a2 : IN std_logic_vector(1 DOWNTO 0) ; oe : OUT std_logic_vector(3 DOWNTO 0)); END ex7; ARCHITECTURE archex7 OF ex7 IS TYPE oe_states IS (idle, choose, banka, bankb, bankc, bankd); ATTRIBUTE state_encoding OF oe_states : TYPE IS gray ; SIGNAL present_state, next_state : oe_states ; SIGNAL oe_out : std_logic_vector(3 DOWNTO 0) ; BEGIN

fsm: PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN IF reset = '1' THEN next_state <= idle; ELSE CASE present_state IS WHEN idle => IF ram = '0' THEN next_state <= choose ; ELSE next_state <= idle ; END IF ; WHEN choose => CASE a3a2 IS WHEN "00" => next_state <= banka ; WHEN "01" => next_state <= bankb ; WHEN "10" => next_state <= bankc ; WHEN "11" => next_state <= bankd ; WHEN OTHERS => next_state <= banka ; END CASE ; WHEN banka => IF eoc = '1' THEN next_state <= bankb ;

WHEN bankb => IF eoc = '1' THEN next_state <= bankc ; ELSE next_state <= idle ; END IF ; WHEN bankc => IF eoc = '1' THEN next_state <= bankd ; WHEN bankd => IF eoc = '1' THEN next_state <= banka ; WHEN OTHERS => next_state <= idle; END CASE; END IF; END PROCESS fsm;

Exercise #7: Solution (contd).
output_logic: PROCESS (next_state) BEGIN CASE next_state IS WHEN idle => oe_out <= "1111" ; WHEN choose => oe_out <= "1111" ; WHEN banka => oe_out <= "1110" ; WHEN bankb => oe_out <= "1101" ; WHEN bankc => oe_out <= "1011" ; WHEN bankd => oe_out <= "0111" ; WHEN OTHERS => oe_out <= "1111" ; END CASE; END PROCESS output_logic ; advance_state: PROCESS (clk) IF clk'EVENT AND clk = '1' THEN present_state <= next_state ; oe <= oe_out ; END IF; END PROCESS ; END archex7;

VHDL User-defined Attributes
VHDL construct which is used to provide information about VHDL objects such as entities, architectures, types, and signals. user-defined attributes are used as synthesis directives to the compiler. These include: state_encoding enum_encoding pin_numbers synthesis_off You can go through these attributes quickly if you are running out of time. All this stuff is in the documentation.

The state_encoding attribute
This is used to specify the state encoding scheme of the FSMs in a VHDL file. The default scheme for CPLDs is sequential. Other schemes such as one_hot_zero and gray encodings are available. TYPE state_type IS (idle,state1,state2,state3); ATTRIBUTE state_encoding OF state_type: TYPE IS sequential;

The enum_encoding Attribute
Used to specify the exact internal encoding to be use for each value of a user-defined enumerated type. Overrides state_encoding in same description. TYPE states IS (idle,state1,state2,state3); ATTRIBUTE enum_encoding OF states: TYPE IS " ";

The pin_numbers attribute
Used to map the external signals of an entity to the pins on the target device Allows the back-annotation of pin placements after synthesis, e.g., LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY counter IS PORT ( clock, reset: IN std_logic; count: OUT std_logic_vector(3 DOWNTO 0) ); ATTRIBUTE pin_numbers OF counter:ENTITY IS "clock:13 reset:2" & " count(3):3 count(2):4 count(1):5 count(0):6"; END counter;

The synthesis_off attribute
Controls the flattening and factoring of signals Makes the signal a factoring point Useful when a signal with a large number of product terms is used in other equations Helpful in cases where substitution causes unacceptable compile time (due to exponentially increasing CPU and memory requirements) Achieves more efficient implementation Should only be used on combinatorial equations Registered equations are natural factoring points

synthesis_off: CPLD Example
An 8-bit comparator controlling a 4-bit, 2-to-1 multiplexer c(7 DOWNTO 0) d(7 DOWNTO 0) 8-bit compare a(3 DOWNTO 0) b(3 DOWNTO 0) x(3 DOWNTO 0) mux

Without synthesis_off
An implementation (without synthesis_off) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mux IS PORT ( a, b: IN std_logic_vector(3 DOWNTO 0); c, d: IN std_logic_vector(7 DOWNTO 0); x: OUT std_logic_vector(3 DOWNTO 0)); END mux; ARCHITECTURE archmux OF mux IS BEGIN x <= a WHEN (c = d) ELSE b; END archmux; Resources used: 1092 product terms, 68 sum splits, 72 macrocells - the comparison is not done on a bit by bit basis

Comparison: with a 4-bit vector
b * c_0 * /d_0 + b * /c_3 * d_3 + b * c_3 * /d_3 + b * /c_2 * d_2 + b * c_2 * /d_2 + b * /c_1 * d_1 + b * c_1 * /d_1 + b * /c_0 * d_0 S_1 = a * c_3 * c_2 * c_1 * /c_0 * d_3 * d_2 * d_1 * /d_0 + a * /c_3 * c_2 * c_1 * /c_0 * /d_3 * d_2 * d_1 * /d_0 + a * c_3 * /c_2 * c_1 * /c_0 * d_3 * /d_2 * d_1 * /d_0 + a * /c_3 * /c_2 * c_1 * /c_0 * /d_3 * /d_2 * d_1 * /d_0 + a * c_3 * c_2 * /c_1 * /c_0 * d_3 * d_2 * /d_1 * /d_0 + a * /c_3 * c_2 * /c_1 * /c_0 * /d_3 * d_2 * /d_1 * /d_0 + a * c_3 * /c_2 * /c_1 * /c_0 * d_3 * /d_2 * /d_1 * /d_0 + a * /c_3 * /c_2 * /c_1 * /c_0 * /d_3 * /d_2 * /d_1 * /d_0 + a * c_3 * c_2 * c_1 * c_0 * d_3 * d_2 * d_1 * d_0 + a * /c_3 * c_2 * c_1 * c_0 * /d_3 * d_2 * d_1 * d_0 + a * c_3 * /c_2 * c_1 * c_0 * d_3 * /d_2 * d_1 * d_0 + a * /c_3 * /c_2 * c_1 * c_0 * /d_3 * /d_2 * d_1 * d_0 + a * c_3 * c_2 * /c_1 * c_0 * d_3 * d_2 * /d_1 * d_0 + a * /c_3 * c_2 * /c_1 * c_0 * /d_3 * d_2 * /d_1 * d_0 + a * c_3 * /c_2 * /c_1 * c_0 * d_3 * /d_2 * /d_1 * d_0 + a * /c_3 * /c_2 * /c_1 * c_0 * /d_3 * /d_2 * /d_1 * d_0 /x0 = /S_1.CMB * /S_2.CMB This is the three equations for x(0) for a 4-std_logic compare (also, the mux inputs are only a and b, not buses). Mention that the equations for the 8-std_logic compare wouldn’t fit on one page.

With synthesis_off A better implementation (with synthesis_off)
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mux IS PORT ( a, b: IN std_logic_vector(3 DOWNTO 0); c, d: IN std_logic_vector(7 DOWNTO 0); x: OUT std_logic_vector(3 DOWNTO 0)); END mux; ARCHITECTURE archmux OF mux IS SIGNAL sel: std_logic; ATTRIBUTE synthesis_off OF sel:SIGNAL is TRUE; BEGIN sel <= '1' WHEN (c = d) ELSE '0'; x <= a WHEN (sel = '1') ELSE b; END archmux; Resources used: 24 product terms, 1 partial result, 5 macrocells

Results with synthesis_off
DESIGN EQUATIONS x_3 = b_3 * /sel.CMB + a_3 * sel.CMB x_2 = /sel.CMB * b_2 + sel.CMB * a_2 x_1 = /sel.CMB * b_1 + sel.CMB * a_1 x_0 = /sel.CMB * b_0 + sel.CMB * a_0 /sel = c_0 * /d_0 + /c_0 * d_0 + c_1 * /d_1 + /c_1 * d_1 + c_2 * /d_2 + /c_2 * d_2 + c_3 * /d_3 + /c_3 * d_3 + c_4 * /d_4 + /c_4 * d_4 + c_5 * /d_5 + /c_5 * d_5 + c_6 * /d_6 + /c_6 * d_6 + c_7 * /d_7 + /c_7 * d_7 the .CMB extension means it is coming from the combinatorial feedback of the macrocell

Third Party Tool Support
CAE Bolt-in Tools Viewlogic Workview Plus/Powerview/WorkView Office (Q1) Mentor (CY3144), Cadence (Q3) Synthesis Tools Synopsys (Q2), Exemplar PLD Development Tools Data I/O Abel 4/5/6 and Synario, MINC, CUPL, LOG/iC, OrCAD PLD Simulation Tools LMG SmartModels All VHDL and Verilog Simulators (with timing) Check your New Product Status Guide for the latest info.

PROGRAMMABLE LOGIC DESIGN WITH VHDL

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