1. Embedded Hardware

2. Embedded System Hardware Embedded system hardware is used for processing sensor input to produce output in task specific fashion Input Interface Information Processing System Output Interface

3. Processors Key requirements: Energy-efficiency High Code Density Microprocessors and Micro-controllers

4. CPU General- Purpose Micro- processor RAMROM I/O Port Timer Serial Port Data Bus Address Bus General-Purpose Microprocessor System Microprocessors CPU for Computers No RAM, ROM, I/O on CPU chip itself Example: Intel’s x86, Motorola’s 680x0 Many chips on mother-board

5. What is Micro-controller? Basically, a micro-controller is a device which integrates a number of the components of a microprocessor system onto a single microchip. A micro-controller combines onto the same microchip: The CPU core Memory (both ROM and RAM) Some parallel digital I/O

6. Micro-controller Source: www.ami.bolton.uk

7. Components of a Micro-controller A Timer module to allow the micro-controller to perform tasks for certain time periods. A serial I/O port to allow data to flow between the micro-controller and other devices such as a PC or another micro- controller. An ADC to allow the micro-controller to accept analogue input data for processing.

8. Micro-controller Source : An Introduction to the design of small-scale embedded systems, Tim Wilmshurst, palgrave 2001

9. Why Micro-controller? Low cost, small packaging Low power consumption Programmable, re-programmable Lots of I/O capabilities Easy integration with circuits For applications in which cost, power and space are critical Single-purpose

10. VonNeuman Architecture Only one bus between CPU and memory RAM and program memory share the same bus and the same memory, and so must have the same bit width Bottleneck: Getting instructions interferes with accessing RAM Program and Data Memory BUS CPU

11. Harvard Architecture Separate program bus and data bus: can be different widths! Instruction Pipelining easy ProgramMemory CPU DataMemory 8-Bits 12/14/16-Bits

12. CISC – Complex Instruction Set Computer A large number of instructions each carrying out a different permutation of the same operation Instructions provide for complex operations Different instructions of different format Different instructions of different length Different addressing modes Requires multiple cycles for execution

13. RISC – Reduced Instruction Set Computer Instructions for simple operations that can be executed in a single cycle Each instruction of fixed length Facilitates instruction pipelining Large general purpose register set Can contain data or address (symmetry) Load-store Architecture No memory access for data processing instructions

14. PIC Architecture PICs are “RISC” Reduced Instruction Set Computer (RISC) Few instructions (usually < 50) Only a few addressing modes Executes 1 instruction in 1 internal clock cycle (Tcyc)

15. The PIC Family: Packages PICs come in a huge variety of packages: Examples: 8 pin : 12C50x (12bit) and 12C67x (14bit) 18pin : 16C5X (12bit), 16Cxxx (14bit) 28pin : 16C5X (12bit), 16Cxxx (14bit) 40pin : 16Cxxx (14bit), 17C4x (16bit) 44 - 68pin :16Cxxx (14bit), 17C4x / 17Cxxx (16bit)

16. PIC Mid-range Block Diagram Ref: PIC architecture reference manual

17. Peripheral Components

18. The PIC Family: Speed PICs require a clock to work.  Can use crystals, clock oscillators, or even an RC circuit.  Some PICs have a built in 4MHz RC clock  Not very accurate, but requires no external components!  Instruction speed = 1/4 clock speed (T cyc = 4 * T clk )  Examples 12C50x 4MHz 12C67x10MHz 16Cxxx20MHz 17C4x / 17C7xxx33MHz 18Cxxx40MHz

19. Clocking Scheme Ref: PIC architecture reference manual

20. Instruction Execution Clock internally divided by 4 to generate 4 quadrature clocks Instruction cycle consist of 4 Q cycles PC incremented every Q1 Instruction is fetched from program and latched into instruction register by Q4 Instruction is decoded and executed in the following Q1 to Q4

21. Instruction Pipelining Fetch takes one cycle, decode and execute takes another cycle While execution, next instruction can be fetched No bus conflict due to Harvard Architecture If instruction changes PC ( e.g. Branch) extra cycle is required to complete instruction

22. Pipelining: Increasing Instruction Throughput 12345678 12345678 12345678 12345678 Fetch-instr. Decode Fetch ops. Execute Store res. 12345678 12345678 12345678 12345678 12345678 Wash Dry Time Non-pipelinedPipelined Time Pipelined pipelined instruction execution non-pipelined dish cleaningpipelined dish cleaning Instruction 1

24. Memory Organization Program Memory Register File Memory

25. The PIC Family: Program Memory PICs have two different types of program storage: 1. EPROM (Erasable Programmable Read Only Memory)  Note: One Time Programmable (OTP) chips are EPROM chips, but with no window!  PIC Examples: Any ‘ C ’ part: 12C50x, 17C7xx, etc. FLASH  Re-writable (even by chip itself)  Much faster to develop on!  Finite number of writes (~100k Writes)  PIC Examples: Any ‘ F ’ part: 16F84, 16F87x, 18Fxxx (future)  PIC program space is different for each chip.

26. Program Memory for your expt. Used for storing compiled code Each location is 14 bits long Every instruction is coded as a 14 bit word Addresses H ’ 000 ’ and H ’ 004 ’ are treated in a special way PC can address up to (8K) addresses for (16F877)

27. The PIC Family: Data Memory PICs use general purpose “ file registers ” for RAM (each register is 8 bits for all PICs) Don ’ t forget, programs are stored in program space (not in data space), so low RAM values are OK. Register File Memory Consist of 2 Components General Purpose Register (GPR) Files (RAM) Special Purpose Register (SPR) files This portion of memory is separated into banks of 128 bytes long 16F877 has 4 banks of register

28. Data Memory 4 banks Important registers ─ STATUS ─ INDF ─ FSR ─ INTCON Use bit 5 and 6 of STATUS (RP0,RP1) to select bank # General purpose registers store user data Registers addressed directly, indirectly W register in accumulator

29. Register Addressing Modes There are 3 types of addressing modes in PIC  Immediate Addressing  Direct Addressing  Indirect Addressing

30. Direct Addressing Uses 7 bits of 14 bit instruction to identify a register file address 8 th and 9 th bit comes from RP0 and RP1 bits of STATUS register.

32. Indirect Addressing Full 8 bit register address is written the special function register FSR INDF is used to get the content of the address pointed by FSR Exp : A sample program to clear RAM locations H ’ 20 ’ – H ’ 2F ’.

34. The PIC Family: Control Registers PICs use a series of “ special function registers ” for controlling peripherals and PIC behaviors. Some examples are: STATUSBank select bits, ALU bits (zero, borrow, carry) INTCONInterrupt control: interrupt enables, flags, etc. TRISTristate control for digital I/O: which pins are ‘ floating ’ TXREGUART transmit register: the next byte to transmit

35. Status Register Status bits ─ Bit 0: Carry ─ Bit 1: Digit carry ─ Bit 2: Zero result ─ Bits 3 & 4: Use at power-up and sleep ─ Bit 5 & 6: bank select ─ Bit 7: bank select for indirect addressing

37. The PIC Family: Peripherals Different PICs have different on-board peripherals Some common peripherals are: Tri-state ( “ floatable ” ) digital I/O pins Analog to Digital Converters (ADC) Serial communications: UART (RS-232C), SPI, I 2 C, CAN Pulse Width Modulation (PWM) Timers and counters Watchdog timers

38. PIC Peripherals: Digital I/O) All PICs have digital I/O pins, called ‘ Ports ’ the 8pin 12C508 has 1 Port with 4 digital I/O pins the 68pin 17C766 has 9 Ports with 66 digital I/O pins Ports have 2 control registers TRISX sets whether each pin is an input or output PORTX sets their output bit levels Most pins have 25mA source/sink (directly drives LEDs)

39. PIC Peripherals: ADCs Only available in 14 bit and 16 bit cores Most 8 bits, newer PICs have 10 or 12 bits Theoretically higher accuracy when PIC is in sleep mode (less digital noise) Can generate an interrupt on ADC conversion done Must wait Tacq to charge up sampling capacitor (see datasheets)

40. PIC Peripherals: Timers Available in all PICs. 14+ bit cores may generate interrupts on timer overflow. Some 8 bits, some 16 bits, some have prescalers Can use external pins as clock in/clock out (ie, for counting events or using a different F osc ) Warning: some peripherals share Timer resources

41. PIC Timers The device has three readable and writeable hardware timers that can increment automatically each instruction cycle (if no prescaler is used). All timers can cause an interrupt on overflow, and then restart from zero

42. PIC Timers / Timer 0 8 bit timer/counter with prescaler Readable and writeable 8-bit software programmable prescaler Internal or external clock set Interrupt on overflow from 0xFF to 0x00 Edge Select for external clock

43. PIC Timers / Timer 1 16-bit timer/counter with prescaler Readable and writeable 1, 2, 4, 8 programmable prescaler Internal or external clock select External clock can be syn. or asyn. Interrupt on overflow Second crystal permitted

44. PIC Timers / Timer 2 8-bit timer/counter with prescaler and postscaler Readable and writeable 1,4 or 16 programmable prescaler 4-bit programmable postscaler Interrupt on overflow Output to port pin

45. Timers TIMER0 is an 8-bit timer with an eight bit prescaler, which can make the timer run 2 to 256 times slower than normal TIMER1 is a 16-bit timer (two 8-bit registers) with a 1:1 to 1:8 prescaler and some other features. Used by given C code to generate soft timer and sound TIMER2 is an 8-bit timer with 1:1 to 1:16 prescaler and a 1:1 to 1:16 postscaler It also has a period register.Used by given C code for PWM motor control Watch Dog Timer

46. PIC Peripherals: CCP Modules Capture/Compare/PWM (CCP) 10 bit PWM width within 8bit PWM period(frequency) Enhanced 16bit cores have better bit widths Frequency/Duty cycle resolution tradeoff 19.5KHz has 10bit resolution 40KHz has 8bit resolution 1MHz has 1bit resolution (makes a 1MHz clock!) Can use PWM to do DAC - See AN655 Capture counts external pin changes Compare will interrupt on when the timer equals the value in a compare register

47. PIC Peripherals: Misc. Sleep Mode: PIC shuts down until external interrupt (or internal timer) wakes it up. Interrupt on pin change: Generate an interrupt when a digital input pin changes state (for example, interrupt on keypress). Watchdog timer: Resets chip if not cleared before overflow Brown out detect: Resets chip at a known voltage level LCD drivers: Drives simple LCD displays VIRTUAL PERIPHERALS: Peripherals programmed in software. USART, timers, and more can be done in software (but it takes most of the resources of the machine)

48. Low End: 12C508 8pin package (DIP, SO) 12bit core - 33 instructions 1us instruction time (Tclk = 4MHz) 512 12bit program memory 25 8bit data memory or registers ( “ File registers ” ) 2 level hardware stack (no interrupts) 5 GPIO pins, 1 input only (25mA source/sink) Features: wake up on pin change, internal oscillator Peripherals: Timer, Watch Dog Timer

49. Mid Range: 16F876 28pin package (DIP, SO) 14bit core - 35 instructions 200ns instruction time (Tclk = 20MHz) 8,092 14bit FLASH program memory 368 8bit data memory or registers (“File registers”) 256 8bit EEPROM (nonvolatile) data registers 8 level hardware stack (interrupts enabled) 22 GPIO (20mA source / 25mA 7sink) Peripherals: 5ch 10bit ADC, USART/I2C/SPI, 16bit & 8bit timers Features: Brown out detect, In-Circuit Debugger (ICD)

50. High End: 17C766 84pin PLCC package 16bit core - 58 instructions 121ns instruction time (Tclk = 33MHz) 16,384 16bit program memory 902 8bit data memory or registers 16 level hardware stack (priority interrupts) 66 GPIO (20mA source / 35mA sink) Peripherals: 2x 16bit + 2x 8bit timer, WDT, 2x USART, 4x CCP, 12ch 10bit ADC

51. 12C508, 16F876, 17C766 Uses 12C508 Inexpensive controllers, glue logic, simple tasks E.g., quadrature decoding, digital interfacing 16F876 Multitasking programs, serial communication E.g., Cheap data acquisition system and digital I/O system for PC off COM ports, data logging 17C766 RTOS, low end DSP, communications, big moosey applications E.g., Rocket Flight Computer, cheap FFT chip

52. Writing PIC Code

53. Word list f any memory location in a microcontroller W work register b bit position in 'f' register d destination bit label group of eight characters which marks the beginning of a part of the program TOS top of stack [] option <> bit position inside register

54. Instruction Format: Four general formats Opcode varies from 3-bits to 6-bits. Variable opcode size allows 35 instructions to be implemented.

56. Instruction Execution Period All instructions are executed in one cycle except for conditional branch instructions if condition was true, or if the contents of program counter was changed by some instruction. In that case, execution requires two instruction cycles, and the second cycle is executed as NOP (No Operation). Four oscillator clocks make up one instruction cycle. If we are using an oscillator with 4MHz frequency, the normal time for executing an instruction is 1 µ s, and in case of conditional branching, execution period is 2 µ s.

57. Instruction Clock

58. Data transfer Transfer of data in a microcontroller is done between work (W) register and an 'f' register that represents any location in internal RAM (regardless whether those are special or general purpose registers). First three instructions (look at the following table) provide for a constant being written in W register (MOVLW is short for MOVe Literal to W), and for data to be copied from W register onto RAM and data from RAM to be copied onto W register (or on the same RAM location, at which point only the status of Z flag changes). Instruction CLRF writes constant 0 in 'f ' register, and CLRW writes constant 0 in register W. SWAPF instruction exchanges places of the 4-bit nibbles field inside a register.

59. Arithmetic and logic PIC like most microcontrollers supports only subtraction and addition. Flags C, DC and Z are set depending on a result of addition or subtraction, but with one exception: since subtraction is performed like addition of a negative value, C flag is inverse following a subtraction. In other words, it is set if operation is possible, and reset if larger number was subtracted from a smaller one. Logic unit of PIC has capability of performing operations AND, OR, EX-OR, complementing (COMF) and rotation (RLF and RRF). Instructions which rotate the register contents move bits inside a register through flag C by one space to the left (toward bit 7), or to the right (toward bit 0). Bit which "comes out" of a register is written in flag C, and value of C flag is written in a bit on the "opposite side" of the register.

60. Bit operations Instructions BCF and BSF perform set or clear one bit anywhere in the memory. Even though this seems like a simple operation, it is executed so that CPU first reads the whole byte, changes one bit in it and then writes in the entire byte at the same place.

61. Directing a program flow GOTO, CALL and RETURN like other microcontrollers, only stack is independent of internal RAM and limited to eight levels. 'RETLW k' instruction is identical with RETURN instruction, except that before coming back from a subprogram a constant defined by instruction operand ‘ k ’ is written in W register. This instruction enables us to design easily the Look-up tables (lists). Mostly we use them by determining data position on our table adding it to the address at which the table begins, and then we read data from that location (which is usually found in program memory). Table can be formed as a subprogram which consists of a series of 'RETLW k' instructions, where 'k' constants are members of the table.

62. Directives Important directives ─ ORG k Place next instruction at location specified by k in program memory Example : ORG 0x10 movlw 0x09 ─ constant EQU value Value is assigned to constant Example : COUNT EQU 0x20 Useful for linking register addresses to variable names ─ END Indicates end of assembly program

63. Software: Assembly Format First column: Labels Second column: opcodes and assembler directives Third Columns & more: operands ; This is a comments since it starts with a “ ; ” ; This program puts out a square wave on PORTA Pin 0 clrfPORTA; Clear PORTA register clrfTRISA; Make PORTA all outputs LoopbsfPORTA,0; Turn on PORTA Pin 0 nop; Match ‘ goto ’ delay nop; “ “ “ bcfPORTA,0; Turn off PORTA Pin 0 gotoLoop; If not zero, loop back

64. Software: Programmers Model Program Memory “Burned” in by programmer (can’t change during execution). Stored instructions, addresses and “literals” (numbers). Hardware Stack Stores addresses for subroutines Program Counter-PCL (PCH) Status Special Purpose Registers I/O pin states, peripheral registers, etc. General Purpose Registers RAM or “data memory”. Variables are stored here. W “Register”

65. Software: Instruction Examples movlw 0xFF Move ( “ mov ” ) the number ( “ l ” for “ literal ” ) 0xFF - that ’ s 256 in decimal- into the working register ( “ w ” ). In other words, load W with the value 0xFF.

66. Software: Programmers Model Program Memory Hardware Stack Program Counter-PCL (PCH) Status Special Purpose Registers General Purpose Registers W “Register” 0xFF

67. Software: Instruction Examples movwf PORTA Move ( “ mov ” ) the working register ( “ w ” ) into the file register ( “ f ” ) named PORTA. In other words, load the register called PORTA with whatever number is in the W register.

68. Software: Programmers Model Program Memory Hardware Stack Program Counter-PCL (PCH) Status Special Purpose Registers PORTA General Purpose Registers W “Register” Value in W

69. Software: Instruction Examples movfPORTA, W Move ( “ mov ” ) the the value of the file register ( “ f ” ) named PORTA into the working register ( “ w ” ). In other words, load W with the whatever number is in PORTA.

70. Software: Programmers Model Program Memory Hardware Stack Program Counter-PCL (PCH) Status Special Purpose Registers PORTA General Purpose Registers W “Register” Value in PORTA

71. Software: Direct Addressing All file registers (RAM) are accessed by an address. This is called direct addressing. For example, movlw0xFF movwf0x06 loads W with FF, and then loads W into GPIO (address 0x06). Thankfully, we can use labels instead of addresses: GPIOequ0x06 movwfGPIO

72. Software: Indirect Addressing Load indirect address into FSR Reading/Writing to INDF acts on address stored in FSR Example code to clear 0x20 - 7F: movlw 0x20 movwf FSR loopclrfINDF incfFSR,F btfssFSR,7 gotoloop INDF 00h 04h 7Fh Register File FSR

73. Microcontroller Basics - Interrupts For time sensitive or randomly occurring events Handled by Interrupt Service Routines in code Common Interrupts External Interrupt Change on pin interrupt Timer interrupts A/D conversion complete interrupt Serial interrupts

74. Interrupts An interrupt is any service request that causes the CPU to stop its current execution stream and to execute an instruction stream that services the interrupt When the CPU finishes servicing the interrupt, it returns to the original execution stream at the point where it left off. Interrupts can be requested from any of the following sources: hardware devices software interrupts (programmed interrupt requests (PIRs))

75. Overview of PIC Interrupts An interrupt is an event which forces a call to a subroutine which is usually referred to as an interrupt service routine Typical sources of interrupts on the PIC include a positive or negative transition on the RB.0/INT input, a change on any of the inputs RB4 - RB7 or a timer / counter overflow from a value of FFH to 00H.

76. Overview of PIC Interrupts the processor saves the return address on the stack and program control is redirected to the interrupt service routine aside from the return address no registers are saved However the user may save such important registers as W and STATUS

77. Overview of PIC Interrupts On interrupt, program flow is directed to program location 004H As a reset directs program flow to 000H On interrupt, a flag bit associated with the type of interrupt is set by the processor flag bits may be used to determine the source of the interrupt and perform the appropriate action

78. Overview of PIC Interrupts a program using interrupts is usually structured as follows ORG 000H ; a reset redirects program to this point GOTO MAIN ORG 004H ; an interrupt redirects the program to here GOTO INT_SERV

79. Overview of PIC Interrupts The user may control the sources of interrupts. For example BSF INTCON, INTE ; enable interrupts on RB0/INT BSF INTCON, RBIE ; enable change in RB4 - RB7 interrupt BSF INTCON, TOIE ; enable timer interrupt Any of these may be used alone

80. Overview of PIC Interrupts At any time in the program, the user may turn any of the sources off by clearing these mask bits BCF INTCON, INTE BCF INTCON, RBIE BCF INTCON, TOIE several sources may be enabled, depending on your application

81. Overview of PIC Interrupts you are ready to accept interrupts. Set the appropriate mask bit (INTE, RBIE or TOIE) and set GIE When no further interrupts are desired, either clear GIE or the mask bits or both On interrupt, the processor clears the GIE bit, inhibiting any further interrupts The bit is set on execution of the return from interrupts (RETFIE) programmer need not perform this book keeping

82. Overview of PIC Interrupts On interrupt, the processor clears the GIE bit, inhibiting any further interrupts The bit is set on execution of the return from interrupts (RETFIE) programmer need not perform this book keeping

83. Overview of PIC Interrupts Note that the occurrence of an interrupt event sets the flag bit It is the user's responsibility to clear the flag bit Failure to clear the flag bit is interpreted by the processor as "a previous interrupt occurred "

84. Basic PIC circuit The minimum set of external components required for the PIC to function are; The master clear pin MCLR is active low and provides a reset feature. Grounding this pin causes the PIC to reset and restart the program stored in the EEPROM. Power and ground are connected to the PIC through pins Vdd and Vss. The dd and ss refer to the drain and source notation used in the PIC. Vdd=5V and Vss=0. The PIC clock frequency can be controlled using an external RC circuit, or a clock crystal. In this case we use either a 4 MHz or 20 MHz clock crystal across OSC1 and OSC2 pins with 18pF capacitors grounded. Serial port is interfaced using MAX202 chip.

85. How do we program the software is written and compiled in a PC and then downloaded to the ROM as machine code. PC must have a compiler to generate the machine code for the micro controller. PIC controllers the programming is done using the windows based program called MPLAB. (www.microchip.com)www.microchip.com Program can be developed using a low-level program (Assembly) Needs experience to program

86. High-level programming Fortunately there are high-level programming tools are available. Can be programmed using C language and compilers are built in to produce machine codes. We use CCS compiler or PICC program (Customer Computer Services Inc., www.ccsinfo.com.www.ccsinfo.com

87. Program memory 13 bit program counter Divided into 4 banks Important locations ─ 0x00 reset vector ─ 0x04 interrupt vector Programs start AFTER 0x04 8 level deep stack

88. Instruction format 3 instruction types Byte oriented - Bit oriented ─ Literal and control Full instruction listing in datasheet and Peatman All instructions take one cycle except conditional

89. Instruction Examples Byte oriented operations ADDWF f,d Add contents of W with register f If d=0 store result in W else store in register f Example : addwf 0x20,0 Can use constants to refer to file registers (recommended) ─ CLRF f Contents of register f are cleared and Z bit (STATUS) is set Example : clrf 0x30 ─ MOVWF f Move data from W register to register f Example : movwf 0x04

90. Instruction Examples Byte oriented operations (contd.) ─ MOVF f,d Move contents of register f to register W (d=0) or itself (d=1) Example : movf 0x20,1 DECFSZ f,d Decrement register f, place result depending on value of d Skip the next instruction if result = zero Example : decfsz 0x20,1 » instruction A » instruction B ─ DECF f,d Decrement f, place result depending on value of d Example : decf 0x30,0

91. Instruction Examples Bit oriented operations ─ BSF f,b Bit b in register f is set to 1 Example : bsf 0x03,5 Manipulate bits of STATUS and INTCON register – enable/disable interrupts, select register banks ─ BTFSC f,b Test bit b of register f, skip next instruction if bit is 0 Skip the next instruction if result = zero Example : btfsc 0x03,2 instruction A instruction B

92. Instruction Examples Literal and control operations ─ ADDLW k Add literal k to register W Example : addlw 0x05 ─ MOVLW k Move literal k into register W Example : movlw 0x21 ─ GOTO k Unconditional branch. Literal k is loaded into PC Example : GOTO THERE Use of labels is recommended

93. Simple Example count equ 0x20;Equate register 0x20 to count org 0x00 ; Initialize reset vector goto start ; org 0x10 ; Actual program starts here start movlw 0x09 ; Move constant to W movwf count ; Move W to count (0x20) loop decfsz count,1 ; Decrement count, skip if zero goto loop ; movlw 0xFF ; If count=0, move 0xFF to W movwf count ; Move 0xFF to count end

94. Software: Relative Addressing PCL = Low byte of the Program Counter Can be read and written. Writing to it sets the address of the next instruction to be executed. 12bit core 14bit core

95. Software: Relative Addressing u Example of Relative Addressing (using a table): ; Here’s a simple lookup table which is called as a ; subroutine. Expects the table offset to be loaded in W. ; An example call looks like this: ;movlw0x04; Load W with 4 ;callTable; Call the table subroutine ;movwfResult; Store the result from the table TableaddwfPCL, W; Jump to (current PCL) + W retlw0x00; Return with 0x00 in W retlw0x23; Return with 0x23 in W retlw0x33; etc. retlw0x88

96. 8051 Microcontroller 1976- Intel MCS-48 (version 8035,8048,8748) 8748- on chip EPROM, 64 bytes RAM, three 8 bits I/O Ports 1980 – Intel launched 8051, took up where ’ 48 left and became firmly embedded in the microcnotroller world. 8051 is one of the most popular microcontrollers in use today despite it ’ s relatively old age Now more than 20 vendors building their own versions of the 8051.

97. 8051 Microcontroller Atmel, Dallas, Philips, Siemen offer controllers based on ‘ 51 core. Philips has many variants 80C51, CMOS version of the 8051. 8052 – is 8051 big brother. A number of additional features which the developer may make use of

98. 80C552 Microcontroller Philips family Within the 80C51 ‘ core ’ Four 8-bit parallel ports Two 16-bit Counter/Timers One UART (Universal Asynchronous Receiver Transmitter)

99. 8051 Microcontroller Extra to 80C51 Core Two 8-bit parallel ports One 16-bit Counter/Timer with Capture and Compare enhancements Two PWM (Pulse Width Modulation) ports One I 2 C (Inter-Integrated Circuit) serial port 256 bytes of static RAM (data memory) Eight-input 10-bit ADC (Analogue to Digital Converter) 8 KB mask programmable ROM (83C552) or 8 KB EPROM (87C552) or without ROM (80C552) + 256 bytes RAM

100. 8XC552 (8051 Core within rectangle) Source : An Introduction to the design of small-scale embedded systems, Tim Wilmshurst, palgrave 2001

101. 8051 Programming Model Source : An Introduction to the design of small-scale embedded systems, Tim Wilmshurst, palgrave 2001

102. PIC microcontroller Late 1970s – General Instruments Corporation produced PIC Microcontroller. Design later taken over by Microchip Inc. PIC one of the fastest moving families in 8 bit arena. Low budget development Developlment tools (h/w & s/w ) chep and readily available.

103. PIC microcontroller family FamilyProgram word size Number of instructions Minimum instruction execution time 12CXXX12/14 bit33/35400 ns 16C5X12-bit33200 ns 16C/FXXX14-bit35200 ns 17CXXX16-bit58120 ns 18CXXX16-bit(enhanced)77100 ns

104. PIC 16F84 Source : An Introduction to the design of small-scale embedded systems, Tim Wilmshurst, palgrave 2001

105. PIC 16F8X Block Diagram Source : An Introduction to the design of small-scale embedded systems, Tim Wilmshurst, palgrave 2001