1. ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 8

2. Intel Information Session Wednesday, October 24th 4:00PM – 5:30PM Memorial Union, Refer to ‘TITU’ for Location Engineering students are invited to attend and learn about exciting full-time and intern opportunities at Intel. Refreshments will be provided. Intel now accepts resumes online at: www.intel.com/jobs/resume www.intel.com/jobs/resume Casual attire is appropriate for all our campus events! We offer internships and full time positions in Washington, Oregon, New Mexico, Arizona, Massachusetts, Colorado, and Northern and Southern California.

3. Intel Open Forum Mike Splinter, Intel Executive VP Director of Sales and Marketing Friday, October 26th 11:30AM – 1:00PM Union South, Refer to ‘TITU’ for Location All Students invited to come and hear about Intel’s current direction and future strategies from a top leader within the company. Questions are encouraged! Biography: Mike is a graduate of the University of Wisconsin, earning both bachelor and master degrees in Electrical Engineering in 1972 and 1974, respectively. Mike joined Intel in 1984 as a Fabrication Manager. He has held various management positions within the company, most notable as Assistant General Manager of the Technology Manufacturing Group and as Executive Vice President and General Manager of the Technology and Manufacturing Group. He was promoted to Senior Vice President in January 1999. He holds two Rockwell patents: one for the quarter micron transistor process, and the other for microwave annealing of implanted junctions.

4. Topics Clock and reset generation. Bus timing. Bus signal de-multiplexing. System buffering Determine suitability of logic family interconnections.

5. System Diagram

6. 80C188EB Package

7. Clock and Reset Clock Generation Internal Oscillator External Oscillator Processor Clock Reset Cold-start vs. warm-start RC reset circuit Microprocessor Supervisors  MAX807 MAX807

8. Bus Cycles Basic Read Cycle Sequence Diagram Basic Write Cycle Sequence Diagram States and Phases Bus Cycle State DiagramDiagram Types of Bus Cycles S2:0 indicate the type of bus cycle in progress.type

9. Bus Cycles 80C188EB Bus Cycle Timing Read Cycle Write Cycle Exercise: What type(s) of bus cycles are run? What address and data during each? 001A001A BA 1000 mov dx, 1000h 001D001D C7 07 1234 mov [bx], 1234h 00210021 8A 07 mov al, [bx] 00230023 EE out dx, al 00240024 ED in ax, dx

10. De-multiplexing Multiplexed Signal Timing Bus signal phases Remote vs. Local De-multiplexing Implementation Devices / Connections Timing  Read Read  Write Write

11. Fully-Buffered System Advantages and Disadvantages Signal Buffering Address bus Data bus  Transceivers  Control signals Control bus Contention issues Terminology Local bus Buffered bus Partial buffering

12. Logic Family Compatibility Logic family characteristics Definitions DC noise margins Driver characteristics Receiver characteristics Compatibility Voltage Current Exercises Capacitive loading TTL to CMOS

13. Wrapping Up Homework #4 due Friday, 10/26/2001

14. 80C188EB Clock Generator

15. MAX807

16. Basic Read Cycle

17. Basic Write Cycle

18. Bus Cycle State Diagram

19. Bus Cycle Types

20. Read Cycle

21. Write Cycle

22. States & Phases

23. 001A BA 1000 mov dx, 1000h

24. 001D C7 07 1234 mov [bx], 1234h

25. 0021 8A 07 mov al, [bx]

26. 0023 EE out dx, al

27. 0024 ED in ax, dx

28. Logic Compatibility Exercises For the following logic families, determine compatibility, noise margins, and fan-out. 74ALS driving 74AC 74AC driving 74ALS V OHmin V IHmin V OLmax V ILmax I OHmax I IHmax I OLmax I ILmax 74ALS2.7V2.0V0.5V0.8V-400uA+20uA+8.0mA-200uA 74AC4.9V 3.76V 0.7*V CC 0.1V 0.7V 0.3*V CC -50uA -24mA +1uA+50uA +24mA -1uA Note: For 74AC, top line is with CMOS load, bottom line is with TTL load.