1. Renesas Electronics America Inc. Confidential May 2011Rev.1.0 Intermediate Low Voltage Power MOSFETs Christopher Lee, PMD & GP Products Group CHRISTOPHER.LEE@RENESAS.COM 408-649-4703

2. Confidential Course Introduction Purpose This course provides intermediate knowledge of low voltage Power MOSFETs. Objective Learn what a power MOSFET is and how it works. Understand how to read a MOSFET datasheet. Understand basic MOSFET characteristics. Content 35 pages (except exam. Session) 5 questions Learning Time 40 minutes

3. MOSFETs © 2010 Renesas Electronics America Inc. All rights reserved. 3 MOSFET’s Packaging Trends Characteristics and Datasheet

4. Confidential What is a Power MOSFET? MOSFET: metal–oxide–semiconductor field-effect transistor MOSFET is a transistor used for amplifying or switching electronic signals In MOSFETs a voltage on the oxide-insulated GATE [G in the diagram below] induces a conducting channel between the two other contacts called SOURCE [S] & DRAIN [D]. Gate voltage is denoted Vg A Power MOSFET can switch and conduct very high power levels, an is useful in power conversion circuits (i.e. boost voltage, decrease voltage, convert DC to AC, etc.) © 2010 Renesas Electronics America Inc. All rights reserved. 4 D G S IDID VGVG D G S

5. Confidential What is a Power MOSFET? The threshold voltage is the minimum V G at which a conducting channel forms. For switching applications such as for switching voltage regulators, the V G is modulated between on (> saturation voltage of the channel) and OFF … For switching applications, this channel between the Drain and Source can be thought of a resistor (R DSON ) that is controlled by the V G in power applications. © 2010 Renesas Electronics America Inc. All rights reserved. 5 D G S IDID VGVG D G S

6. Packaging Trends in LV MOSFETs 6 MOSFET’s Packaging Trends Characteristics and Datasheet

7. Confidential SMD Packages

8. Confidential Footprint Compatibility 8 Solutions from Renesas : (LFPAK/LFPAK-i, WPAK) + WINFET/BEAM MOSFETs Renesas (H ita chi, NXP) Bottom Side CoolingDouble-Sided Cooling LFPAK-i S S S G Top D D LFPAK-i S S S G Top D D Renesas – LFPAK-i IR – DirectFET Bottom D WPAK Bottom

9. Confidential Space Saving Packages QFN56QFN40 SOP-8 WPAK LFPAKLFPAK-i WPAK-Dual HVSON mini-HVSON HWSON3044 HWSON3030 Vin Vout Vcc L Driver / Controller Hi Lo [ 5x6 ] [ 3.3x3.3 ] [ 5x6 ] [ 3x4.4 ] [ 6x6 ] [ 8x8 ] Integrated Power IC Compounded Hi/Lo MOSFETs Down sizing -56% (5x6 ->3x4.4) -44% (8x8 ->6x6) -64% (5x6 ->3.3x3.3) -50% (5x6x2 ->5x6x1) -29% (5x6x3 ->8x8) Down sizing Down sizing 9 © 2010 Renesas Electronics America Inc. All rights reserved.

10. Confidential 10 Package Roadmap for High Current Application

11. Confidential Package Resistance 11 © 2010 Renesas Electronics America Inc. All rights reserved.

12. Confidential Observed Trend Toward Integration 12 - Another Solution from Renesas - 12Vin Controller CPU DISBL VCIN REG5V VIN PGND VLDRV PWM VSWH Overlap Protect. GH CGND BOOT SBD GL 3-state Input REG5V UVL A “System in Package”, SiP Driver QFN40 [ 6x6 ] Top view Bottom View [ 8x8 ] QFN56 Down sizing

13. © 2010 Renesas Electronics America Inc. All rights reserved. 13 Characteristics & Datasheet MOSFET’s Packaging Trends Characteristics and Datasheet

14. Confidential © 2010 Renesas Electronics America Inc. All rights reserved. 14 MOSFET Characteristics Break down voltages (V DSS, V GSS ) On Resistance (R DSON ) Switching chacteristics Gate Charge (Q G, Q GD ) Capacitances (C ISS, C OSS, etc) Avalanche Body Diode ASO  Area of Safe Operation

15. Confidential Power MOSFET Absolute Maximum Ratings 15 © 2010 Renesas Electronics America Inc. All rights reserved.

16. Confidential Gate to Source Leak Current Gate Source Cutoff Voltage Forward Transfer Admittance Drain Source on Resistance 1 Drain Source on Resistance 2 Input Capacitance Output Capacitance Reverse Transfer Capacitance V DSS I DSS I GSS V GS(off) IY fs I (g m ) R DS(on)1 R DS(on)2 C ISS C OSS C RSS Min Typ Max 60 - - - - 10 - -  0.1 1.0 - 2.5 55 90 - - 4.3 5.5 - 6.0 9.0 - 9770 - - 1340 - - 470 - I D =10mA, V GS =0 V DS =60V, V GS =0 V GS =  20V, V DS =0 V DS =10V, I D =1mA I D =45A, V DS =10V I D =45A, V GS =10V I D =45A, V GS =4V V DS =10V V GS =0 F SW =1MHz Parameter Symbol Value Test Condition Temperature Dependence Attention for Design (Ta=25degC) : Have positive temperature coefficient. : Have negative temperature coefficient. There is a V DS dependency here. Indicate drive loss at operating time of analog There is V DS dependency. Influence on fall time t f at light load time. There is V DS dependency. Influence on SW time t r and t f Influence on noise at operating time of SW and SW time t r and t f It is related to on-resistance High dependence on temperature, but low loss Protection diode built in products are from scores of nA to scores of  A. The guarantee is  10uA. This is the most important parameter to decide on-loss. Pay attention to rise in curve with temperature Unit V uA V S m  pF Drain-source destruction voltage Zero Gate Voltage Drain Current Note: V DS(off) = V TH S = siemens = 1/ C ISS = C GS + C GD C OSS = C DS + C GD C RSS = C GD MOSFET Electrical Characteristics 16 © 2010 Renesas Electronics America Inc. All rights reserved.

17. Confidential Important MOSFET Device Design Parameters R DS(si) = R ch + R epi + R sub Structure of N-Channel Trench Cell N ++ N - N + P+ D S G Epi Substrate R GI © 2010 Renesas Electronics America Inc. All rights reserved. 17 R DS(si) Drain Gate Source R WIRE RGRG Parasitic NPN Bipolar Transistor R GI R sub R epi R ch MOSFET Resistances Body Diode V GSS V DSS

18. Confidential V DSS 30V200V60V R ch R epi R sub 30% 40% 30% 10% 80% 10% 5% 94% 1% The Resistive Components of the overall R DS(on) Structure of a Vertical Power MOSFET R DS(ON) = R ch + R epi + R sub + R WIRE Resistance ratio for Trench MOSFET Vertical MOSFET Cells Overall R DS(on) Components 18 © 2010 Renesas Electronics America Inc. All rights reserved. Drain of the Si is glued to the tab with silver epoxy, so the contribution of that resistance is negligible Return

19. Confidential R DS(ON) - T C characteristic (2SK3418) Temperature dependency of On-Resistance, R DS(ON) 19 © 2010 Renesas Electronics America Inc. All rights reserved.

20. Confidential Important MOSFET Device Design Parameters Structure of N-Channel Trench Cell N ++ N - N + P+ D S G Epi Substrate Rgi © 2010 Renesas Electronics America Inc. All rights reserved. 20 MOSFET Package Parasitic R WIRE Packaging

21. Confidential Important MOSFET Device Design Parameters C ISS = C GS + C GD C OSS = C DS + C GD C RSS = C GD Structure of N-Channel Trench Cell N ++ N - N + P+ D S G Epi Substrate Rgi © 2010 Renesas Electronics America Inc. All rights reserved. 21 C GS C DS Drain Gate Source C GD MOSFET Capacitances V GSS V DSS

22. Confidential Important MOSFET Device Design Parameters Structure of N-Channel Trench Cell N ++ N - N + P+ D S G Epi Substrate Rgi © 2010 Renesas Electronics America Inc. All rights reserved. 22 MOSFET Body Diode

23. Confidential The Characteristics of a MOSFET Body Diode I DR - V SD characteristic (2SK3418) (N-channel) = 0 V 1.A parasitic body diode is built in the Power MOSFET between the source and drain. The maximum current rating of this diode, I DR, is the same value as the maximum rating of the MOSFET forward drain current, I D 2.This diode shows that it has the same characteristic for forward voltage as an ordinary diode in the case of zero bias for the gate drive voltage, V GS =0 3.If the gate drive voltage, V GS, has a positive bias, as in the case of N-channel MOSFET. Then, V SD will be a voltage that is determined by the on-resistance R DS(on) (V SD = I D x R DS(on) ), as shown on the figure to the right. Therefore, it is possible to get very low forward voltage similar to a Schottky barrier diode (SBD). 4.By taking advantage of such a characteristic, the body diode can be used to benefit the application in the following: a)Load switches for protection against reverse connection of battery b)Hot swap circuits of redundant method for switching power supply (n+1) c)Replace external diodes in motor driving circuit bridges d)Secondary synchronous rectifier circuits in switching power supplies 23 © 2010 Renesas Electronics America Inc. All rights reserved.

24. Confidential Schottky Barrier Diode Non-overlap/Dead Time to avoid cross conduction (“shoot-through”) Body diode of a synchronous switch conducts during dead time Body diode is lossy and is slow to turn on/off A Schottky diode (SBD) is used in parallel with the MOSFET Reduced the forward voltage drop from ~0.7V to ~0.2V Reduces losses from body diode turn on and reverse recovery losses Limits overshoot on turn on Non-overlap time conduction can be significant at high switching frequencies © 2010 Renesas Electronics America Inc. All rights reserved. 24 Gate Source Drain SBD Body Diode

25. Confidential SBD Reduces Turn-on Spike Noise V P =22.6V -17% Vds(L) Vg(H) Vgs(L) Suppressing Spike voltage V P =27.2V Lo:RJK0351DPA (without SBD) Vds(L) Vgs(L) Vg(H) Built in SBD Lo:RJK0381DPA (Built in SBD)

26. Confidential Drain-Source Saturation Voltage, V DS(ON) V DS(on) - V GS characteristic (2SK3418) V DS(ON) depends on the Gate Drive Voltage, V GS, and the Drain current, I D V DS(ON) = I D x R DS(ON) 26 © 2010 Renesas Electronics America Inc. All rights reserved.

27. Confidential 1.Total gate charge, Q G, is the point where the gate driving voltage, V GS, becomes equal to the Driver output voltage (DV GS ) at the gate of the MOSFET 2.Q G is the parameter that controls gate peak current, I G(peak), from the MOSFET driver and the drive loss, P(drive loss) I G(peak) = Q G /t (1) P(drive loss) = F SW *Q G *V GS (2) 3.Q GD corresponds to mirror capacitance, C RSS and its value depends on the power supply voltage V DS. Recall that C RSS = C GD 4.Q GD is the parameter that greatly influences a devices switching fall time, t f, + where R S = R DRIVER, R G = R PCB +Rgi: 5.The fall time, t f, controls the switching loss and t f is computed using formula (3) above. Both Q G and Q GD are important items when designing for high frequency operation. For high-speed switching (over F SW =100kHz) applications, the smaller the R ON /Q G or R ON /Q GD the more efficiency the MOSFET device will become Q G, Q GD, ig(peak), P(Drive Loss) & Fall Time (t f ) definitions. t f = V GS(on) - V TH ln V GS(on) (R S + r g )*Q GD V TH (3).. Input Dynamic Characteristic (2SK3418) V GS (V) Gate Charge (a) Q G @ (V GS =DV GS ) Q TH Q GD V DS (V) V DS V GS V TH V GS(on) Q GS QGQG DV GS Q = C ISS V GS = integral (I G * dt) = I*t = I*1/F SW I = Q*F SW P= IV =Q*F SW *V = C*F SW *V 2 27 © 2010 Renesas Electronics America Inc. All rights reserved.

28. Confidential Avalanche Breakdown It is a phenomenon that can occur in both insulating and semiconductor materials. It is a form of electric current multiplication that can allow very large currents to flow within materials which are otherwise good insulators. It is a type of electron avalanche. The Avalanche process occurs when the carriers in the transition region are accelerated by the electric field to energies sufficient to free electron-hole pairs via collisions with bond electrons. © 2010 Renesas Electronics America Inc. All rights reserved. 28

29. Confidential Avalanche - Destruction Failure Modes When the current through the output inductor is quickly turned off, the magnetic field of the inductor induces a counter electromagnetic force, EMF, that can build up a high V DS voltage across the MOSFET. The full buildup of this induced voltage may exceed the rated breakdown voltage, VDSS, of the MOSFET and result in the catastrophic failure of the MOSFET. Two failure modes exist when MOSFETs are subjected to unclamped inductive switching, UIS. These two failure mechanisms are defined as either 1) the active Mode 1 or 2) the passive Mode 2. 1.The first, or active Mode 1, results when the avalanche current actively forces the parasitic bipolar transistor into conduction and turns it on. Today, MOSFETs are being manufactured in which the parasitic bipolar transistor never turns on and Mode 1 failures do not occur 2.The second, or passive Mode 2, results when the instantaneous chip temperature reaches a critical value. At this elevated temperature, a “meso-plasma” forms within the parasitic NPN bipolar transistor and causes catastrophic thermal runaway. The passive mechanism is, therefore, identified as that failure mode not directly attributed to avalanche currents. In either of the first or the second cases, the MOSFET is destroyed. Parasitic Bipolar Transistor 29 © 2010 Renesas Electronics America Inc. All rights reserved. V IN V OUT I OUT L C D ILIL

30. Confidential 12345 Safe Operation Area, SOA, Definitions SOA for the (2SK3418) 30 © 2010 Renesas Electronics America Inc. All rights reserved.

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