1. Overview of Intel Architecture Intel SSG/SSD/UEFI

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3. Agenda Intel Architecture Intel and Process Technologies Core and Atom architecture Basic computer architecture Interconnect and threads Memory subsystem I/O subsystem and Interrupt

4. Core Count/Proc: 1 – 8 Max TDP/Proc: 0.65W – 130W Spectrum of Computing on Intel Architecture Intel's Smallest Processor Built with the World's Smallest Transistors The Fastest Processor on the Planet The Greatest Intel® Xeon® Performance Leap In History DesktopLaptop Enterprise Server High-Performance Computing Internet Data Center HandheldCEEmbeddedNetbook INTERNET-CONNECTED DEVICES PC CLIENTS SERVERS IA maintains the Computing Continuum

5. Innovation-Enabled Technology Pipeline Researchers are moving on to Investigation of Novel Technology Options

6. Intel Platform Architecture Mainstream PC and ServerTickTockTickTock 45nm32nm PenrynNehalemWestmereSandybridge Refined μ -architecture New μ -architecture Tick-Tock model remains the foundation for mainstream processors

7. Intel’s Second Platform Architecture Internet Connected Devices45nm32nm22nm Intel® ATOM™ Processor Cores 15nm System-on-ChipProducts Saltwell New Core So c Bonnell Connecting the World with IA

8. MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME Processor Where calculations and decisions take place. – Calculations: Arithmetic operations Repetitive operations Increment/decrement – Decisions: True/false conditions – Where to store data Correct routines to run Performance is set by internal fusing of its clock speed and driven as a multiplier of the Front Side Bus speed FSB connects it to the MCH (or ‘North Bridge’)

9. GMCH Also called “Northbridge” MCH = Memory Controller Hub Graphics & Memory Controller Hub GMCH contains – integrated graphics device (IGD) – integrated memory controller (IMC) – Manageability Engine controller (ME) Manages the flow of information between – the processor interface – the System Memory interface – the External Graphics via a PCI Express – internal graphics interfaces – the ICH through DMI interface. Communicates with the South Bridge via the Direct Media Interface (DMI). Controls all transfers to main memory Supports PCI Express based external graphics and devices. GMCH - Controls graphics data either used by a plug in graphics card or produces signals to directly control the display MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

10. Front Side Bus (Host Bus) The communications channel between the processor and North Bridge Also referred to as the Front Side Bus (FSB) Transfers data up to 6.4 Gbytes/sec MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

11. ICH Also called “Southbridge” I/O Controller Hub Progressive evolution of system control features from ICH2 to ICH10 ICH10 controls over 22 distinct system functions and busses Controls all data to be ultimately passed to Input / Output Devices (other than the display) including Audio Controller Hard Drives CD ROM Drives PCI & PCI express cards USB devices Controls data flow to components on the LPC bus FWH SIO TPM MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

12. Direct Media Interface A proprietary chip-to-chip connection between the (G)MCH and ICH. – Not shared with any other components – Similar to PCIe Functionality is software transparent Is based on the standard PCI Express specification. Up to 1 Gbyte/sec transfer rate First used in ICH6 approx 2004 MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

13. System Memory Interface Used by the North Bridge to transfer data to and from the DIMMs – Transfer rate depends memory technology up to 10.7 GBytes/sec Faster data movement improves the efficiency of the processor Dual-channel memory allows the memory controller move double the amount of data that it could normally move with single-channel memory Directly supports one or two channels of DDR2 or DDR3 memory with a maximum of two DIMMs per channel MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

14. System Monitor & System Management Bus System Monitor ( sometimes referred to as Heceta chip) monitors critical system voltages and temperatures – Main system voltages – Processor voltage & temperature – Ambient air temperature inside computer case Also controls processor and case fan speeds System Management Bus (SMB) is used to access devices where only a minimal amount of data needs to be transferred – Clock Generator – System Monitor SMB is a two wire serial bus – a clock line and a data line – 100 Kbits/s to 12.5 Kbyte/s – Used as alternate path to devices for configuration during boot-up DIMMs PCI and PCIe cards MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

15. Voltage Regulator Module (VRM) VRM output determined by Voltage Identification fuses (VID) in the processor – Changing processor will change VRM output if VID requirements are different Voltage regulation is critical to the processor and many other system components. The processor has it’s own regulator which is monitored by the Heceta System Monitor. VRM and other regulators are used to supply various system voltages. MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

16. System Peripheral Interface (SPI) FLASH Memory Serial Peripheral Interface (SPI) bus transfers data from the South Bridge to Flash ROM and LAN Controller – Provides faster access to BIOS than the LPC bus – Up to 1Gbyte/sec Flash Read Only Memory (ROM) is an alternative location for BIOS – Can store more data than FWH – Faster access for the Processor than the FWH – Note it’s closer proximity to the processor Info stored in the Flash is non-volatile Can also store data used by the LAN controller SPI is required for ME-enabled systems MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLA SH SPI FLA SH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

17. Manageability Engine (ME) Manageability Engine (ME) in the MCH is a microcontroller like the embedded controller (EC). Manageability functions incorporated into ICH. Manageability firmware is independent of system BIOS and Operating System. Manageability functions powered separately – Allows for functionality in suspend states (when supported) – Out Of Band (OOB) communication can operate independent of standard busses Implementation and functionality varies from platform to platform. MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

18. PCI Express & PCI PCI Express (PCIe) – Multi-channel serial bus – Transfers 4 Gbit/sec per channel – Various bus widths x1 & x4 - general peripheral cards e.g. LAN controllers, MODEMs, and audio x16 - Video display apps (64 Gbit/sec or 8 Gbyte/sec) – Destined to replace PCI – versatile & adaptable to many different applications Peripheral Component Interconnect (PCI) – General purpose I/O bus for peripheral plug in cards e.g. LAN controllers MODEM cards Audio controllers – Transfers up to 132 Mbytes / sec MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

19. High Definition (HD) Audio High Definition Audio Controller provides for versatile audio performance Often includes Surround Sound Allows for multiple input devices – Microphone – External CD players – Other audio sources MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HD A Cod ec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

20. LAN A Gigabit Local Area Network controller (Gb LAN) Controller. Transfers up to 1 Gigabit/sec Transceiver interface to physical layer Used in network applications where either traditional LAN cables are used or with fiber optic applications Connects to ICH – via LCI (LAN Control Interface) for low speed – via GLCI (Gigabit LAN Control Interface) for high speed Note -GLCI is fed from a PCIe bus MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LA N HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

21. Data Storage and Transfer PATA – Parallel ATA storage interface for connecting hard disk drives, solid state devices and CD/DVD drives; also called IDE SATA – Serial ATA storage interface which replaces older (slower/bulkier) PATA systems USB – Universal Serial Bus used to connect peripherals to the PC with features like Plug and Play Others not shown include – Firewire – (IEEE 1394) Serial bus interface meant for high speed data transfers - targeted for audio, video and storage uses – Serial port (RS232) – Recommended Standard 232 is an older (slower/bulkier) peripheral connection port, replaced by USB – Parallel port (IEEE1284) – An older (slower/bulkier) peripheral connection port targeted for printer use, replaced by USB MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

22. LPC Bus Low Pin Count (LPC) bus is used to transfer data between the South Bridge and the FWH, SIO and TPM. Small bus – takes little space on board Rather slow: Transfer rate up to 16 Mbytes/sec MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

23. Trusted Platform Module (TPM) A security device included on some desktop boards. Provides encryption for transferring data over the internet. Provides positive identification for computers in network environments. Complies with US Department of Homeland Security Specifications. Certain ICH SKUs (ICH10 corporate) integrate the TPM into the ICH. MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TP M FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

24. Super I/O (SIO) Controller Controls Legacy I/O Interfaces – Keyboard – Mouse – Floppy drives – Serial and Parallel Ports These interfaces can all be replaced with a single standard interface called the Universal Serial Bus (USB) The SIO also controls a number of miscellaneous system functions: – Power management – Reset sequencing MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

25. Firmware Hub The FWH is a memory component where the Basic Input Output System (BIOS) is stored – Designers may choose from a wide variety of components so each desktop board design will have it’s own BIOS – Info stored in the FWH is non- volatile ( retained when powered off) – Allows BIOS to be available at power-up so the processor is able to configure the system. – A system can have a FWH or SPI or both MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FW H SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME

27. Component Placement Example Intel DQ45CB Board MCH or GMCH MCH or GMCH ICH LCI PCI DMI GLCI FSB USB PCIe 16x Graphics SPI SATA IDE DIMMS Mem Bus DVI HDMI Video Codec Video Codec Processor SPI FLASH SPI FLASH TPM FWH SIO gB LAN HDA Codec PCIe VRM Heceta Clock Gen Clock Gen USB PCIe/PCI DMI FSB BUS slot Connector Component in-chipset function SM Bus... LPC (GMCH) IGD IMC ME SPI FLASH Gb LAN HDA Video CODECs 1394 ICH Mem Bus CPU GMCH CPU VReg FSB Clock SIO

28. Headers & Connectors Example Intel DQ45CB Board

29. Intel QuickPath Architecture

30. Intel Core Processor overview

31. IA Platform Capabilities  Intel Architecture capable of QPI connected 8-Sockets/128 threads  Scalable systems and greater than 8-socket capability with OEM node controllers  Twisted Hypercube Interconnection  Max 2 QPI hops between two sockets IA Platforms Deliver Ample Threads

32. Inter-Connection Architecture Symmetric Multi Processing (SMP)

33. Inter-Connection Architecture Non Uniform Memory Architecture (NUMA)

34. I/O Subsystem and Interrupt