1. Low-Noise Amplifier

2. RF Receiver Antenna BPF1 LNA BPF2 Mixer BPF3 IF Amp Demodulator
RF front end LO

3. Low-Noise Amplifier First gain stage in receiver
Amplify weak signal
Significant impact on noise performance
Dominate input-referred noise of front end
Impedance matching
Efficient power transfer
Better noise performance
Stable circuit

4. LNA Design Consideration
Noise performance
Power transfer
Impedance matching
Power consumption
Bandwidth
Stability
Linearity

5. Noise Figure Definition As a function of device
G: Power gain of the device

6. NF of Cascaded Stages Overall NF dominated by NF1
Sin/Nin
Sout/Nout
G1, N1, NF1
Gi, Ni, NFi
GK, NK, NFK
Overall NF dominated by NF1
[1] F. Friis, “Noise Figure of Radio Receivers,” Proc. IRE, Vol. 32, pp , July 1944.

7. Simple Model of Noise in MOSFET
Flicker noise
Dominant at low frequency
Thermal noise
g: empirical constant
2/3 for long channel
much larger for short channel
PMOS has less thermal noise
Input-inferred noise Vg Id Vi

8. Thermal noise dominant
Noise Approximation
Noise spectral density
1/f noise
Thermal noise dominant
Thermal noise
Frequency
Band of interest

9. Power Transfer and Impedance Matching
Power delivered to load
Maxim available power Rs
jXs
jXL Vs I V RL
Impedance matching
Load and source impedances conjugate pair
Real part matched to 50 ohm

10. Available Power
Equal power on load and source resistors

11. Reflection CoefficientRs
jXs
jXL Vs I V RL

12. Reflection Coefficient
No reflection Maximum power transfer

13. S-Parameters Parameters for two-port system analysis
Suitable for distributive elements
Inputs and outputs expressed in powers
Transmission coefficients
Reflection coefficients

14. S-Parameters a1 b2
S21
S11
S22
S12 b1 a2

15. S-Parameters
S11 – input reflection coefficient with the output matched
S21 – forward transmission gain or loss
S12 – reverse transmission or isolation
S22 – output reflection coefficient with the input matched

16. S-Parameters I1 I2 S Z1 Z2
Vs1 V1 V2
Vs2

17. Stability Condition
Necessary condition
where
Stable iff

18. A First LNA Example Assume Effective transconductance io
No flicker noise
ro = infinity
Cgd = 0
Reasonable for appropriate bandwidth
Effective transconductance Rs Vs Rs
4kTRs Vs
Vgs
gmVgs
4kTggm

19. Power Gain
Voltage input
Current output

20. Noise Figure Calculation
Power output
Device noise + input-induced noise
Input-induced noise

21. Unity Current Gain Frequency
Device
iout
iin Ai fT
0dB
frequency f

22. Small-Signal Model of MOSFET
Cgs
Cgd
rds
Cdb
Rg: Gate resistance
ri: Channel charging resistance V1 V2 i1 i2 Rg
Cgd
Cdb
Cgs
V’gs V2
rds V1 ri
gmV’gs

23. wT Calculation i1 i2 V’gs gmV’gs Cgd i1 i2 ri Cgs Rg V1 Rg Cgd Cdb Cgs
rds V1 ri

24. wT of NMOS and PMOS 0.25um CMOS Process* Set: Solve for wT
[2] Tajinder Manku, “Microwave CMOS - Device Physics and Design,” IEEE J. Solid-State Circuits, vol. 34, pp , March 1999.

25. Noise Performance Low frequency CMOS technology Rsgm >> g ~ 1
gm >> Rs = 50 ohm
Power consuming
CMOS technology
gm/ID lower than other tech
wT lower than other tech

26. Review of First Example
No impedance matching
Capacitive input impedance
Output not matched
Power transfer
S11=(1-sRCgs)/(1+sRCgs)
S21=2Rgm/(1+sRCgs), R=Rs=RL
Power consumption
High power for NF
High power for S21

27. Impedance Matching for LNA
Resistive termination
Series-shunt feedback
Common-gate connection
Inductor degeneration

28. Resistive TerminationRs
4kTggm
4kT/Rs
4kT/RI Vs RI Is Rs RI
Vgs
gmVgs
Current-current power gain
Noise figure

29. Comparison with Previous Example
Resistive-termination
Introduced by input resistance
Signal attenuated

30. Summary - Resistive Termination
Noise performance
Low-frequency approximation
Input matched Rs = RI = R
Broadband input match
Attenuate signal
Introduce noise due to RI
NF > 3 dB (best case)

31. Series-Shunt FeedbackRF
Broadband matching
Could be noisy RL Rs Vs Ra
iout Rs RF RL
Cgs
Vgs
gmVgs Vs Ra

32. Common-Gate Structure
4kTggm RL Rs RL Rs
4kTRs
gmVgs Vs
Vgs RL Rs
4kTRs gm Vs
Vgs
gmVgs
4kTggm

33. Input Impedance of CG Structure
Yin=gm+sCgs
Input-impedance matching
Low frequency approximation
Direct without passive components
1/gm=Rs=50 ohm

34. Noise Performance of CG Structure
Signal attenuated

35. Power Transfer of CG Structure
Rs = RL = R = 50 ohm
S11=0, Low frequency

36. Summary – CG Structure Noise performance Impedance matching
No extra resistive noise source
Independent of power consumption
Impedance matching
Broadband input matching
No passive components
Power consumption
gm=1/50
Power transfer

37. Inductor Degeneration Structure
Zin
iout Rs Lg Rs Lg
iin
Cgs
Vgs
gmVgs Vs
Vin Ls Vs Ls
Zin

38. Input Matching for ID Structure
Zin
iout Rs Ls Lg
Cgs
Vgs
gmVgs
gmLs/Cgs Vs
Zin=Rs
IM{Zin}=0
RE{Zin}=Rs

39. Effective Transconductance
Zin
iout Rs Ls Lg
Cgs
Vgs
gmVgs
gmLs/Cgs Vs

40. Noise Factor of ID Structure
= w0
Calculate NF at w0

41. Input Quality Factor of ID StructureV Rs Ls Lg
Cgs
gmLs/Cgs Vs

42. Noise Factor of ID Structure
Increase power transfer
gmLs/Cgs = Rs
Decrease NF
gmLs/Cgs = 0
Conflict between
Power transfer
Noise performance

43. Further Discussion on NFw0
w2 ~= 1/Cgs/(Lg+Ls)
Input impedance matched to Rs
RsCgs=gmLs
Suitable for hand calculation and design
Large Lg and small Ls

44. Power Transfer of ID Structure
Rs = RL = R = 50 ohm @

45. Computing Av without S-ParaRs Lg Vs Ls

46. Power Consumption

47. Power Consumption Technology constant Standard specification
L: minimum feature size
m: mobility, avoid mobility saturation region
Standard specification
Rs: source impedance
w0: carrier frequency
Circuit parameter
Lg, Ls: gate and source degeneration inductance

48. Summary of ID Structure
Noise performance
No resistive noise source
Large Lg
Impedance matching
Matched at carrier frequency
Applicable to wideband application, S11<-10dB
Power transfer
Narrowband
Increase with gm
Power consumption

49. Cascode Isolation to improve S12 @ high frequency
Small range at Vd1
Reduced feedback effect of Cgd
Improve noise performance LL Vo
Vbias M2
Vd1 Rs Lg M1 Vs Ls

50. Rs Vs Ls Lg LL M1 Vo
Vgs
gmVgs
Cgs

51. LNA Design Example (1) Vdd Cb2 Lvdd Lb2 Vout M4 Output bias Ld Lout
Vbias M3 M2
Lb1 Tm Rs M1 Lg
Lgnd
Cb1 Vs Cm Ls
Input bias
Off-chip matching
[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits,  vol. 32, pp. 745 – 759, May 1997.

52. LNA Design Example (1) Supply filtering Lvdd M4 Ld Lout Vbias M3 M2
Lb1 Tm Rs M1 Lg
Lgnd
Cb1 Vs Cm Ls
Unwanted parasitics
[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits,  vol. 32, pp. 745 – 759, May 1997.

53. Circuit Details Two-stage cascoded structure in 0.6 mm First stage
W1 = 403 mm determined from NF
Ls accurate value, bondwire inductance
Ld = 7nH, resonating with cap at drain of M2
Second
4.6 dB gain
W3 = 200 mm

55. LNA Design Example (2) NF = 1 + K/gm gm = gm1 + gm2 IB1 M2 Vout1 RB NL
IREF RX M4
VB1
VRF Ns
Off-chip matching M1 M5 Cs CX
Off-chip matching M7 CB M3 M6
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec

56. Simplified view

57. LNA Design Example (2) IB1 M8 M2 Vout1 RB NL IREF RX M4 VB1 VRF Ns M1Cs CX M7 CB M3 M6
Bias feedback
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec

58. LNA Design Example (2) IB1 M8 M2 Vout1 RB NL IREF RX M4 VB1 VRF Ns M1Cs CX M7 CB M3 M6
Bias feedback
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec

59. LNA Design Example (2) VA IB1 M8 M2 Vout1 RB NL IREF RX M4 VB1 VRF NsCs CX M7 CB M3 M6
Bias feedback
DC output = VB1
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec

61. LNA Design Example (3)
Objective is to design tunable RF LNA that would:
Operate over very wide frequency range with very fine selectivity
Achieve a good noise performance
Have a good linearity performance
Consume minimum power

62. LNA Architecture
The cascode architecture provides a good input – output isolation
Transistor M2 isolates the Miller capacitance
Input Impedance is obtained using the source degeneration inductor Ls
Gate inductor Lg sets the resonant frequency
The tuning granularity is achieved by the output matching network
VDD R1 LD M3
Matching Network R2 M2
Output to Mixer M1 LG
Input to LNA LS

63. Matching Network
The output matching tuning network is composed of a varactor and an inductor.
The LC network is used to convert the load impedance into the input impedance of the subsequent stage.
A well designed matching network allows for a maximum power transfer to the load.
By varying the DC voltage applied to the varactor, the output frequency is tuned to a different frequency.

64. Simulation Results - S11
The input return loss S11 is less than – 10dB at a frequency range between 1.4 GHz and 2GHz
Input return loss

65. Simulation results - NF
The noise figure is 1.8 dB at 1.4 GHz and rises to 3.4 dB at 2 GHz.
Noise Figure

66. Simulation Results - S22
By controlling the voltage applied to the varactor the output frequency is tuned by 2.5 MHz.
The output return loss at 1.77 GHz is – dB and the output return loss at GHz – dB.
S22 at 1.77 GHz
S22 at GHz

67. Simulation Results - S22
The output return loss at 2 GHz is – dB and the output return loss at GHz – 26.6 dB.
S22 at GHz
S22 at 2 GHz

68. Simulation Results - S21 The overall gain of the LNA is 12 dB
S21 at GHz

69. Simulation Results - Linearity
The third order input intercept is –3.16 dBm
-1 dB compression point ( the output level at which the actual gain departs from the theoretical gain) is –12 dBm
-1dB compression point
IIP3

70. Not accurate for low voltage short channel devices
From an earlier slide:
Flicker noise
Dominant at low frequency
Thermal noise
g: empirical constant
2/3 for long channel
much larger for short channel
PMOS has less thermal noise
Input-inferred noise Vg Id Vi
Not accurate for low voltage short channel devices

71. Modifications Thermonoise g is called excess noise factor
= 2/3 in long channel
= 2 to 3 (or higher!) in short channel NMOS (less in PMOS)

72. gdo vs gm in short channel

73. gdo vs gm in short channel

74. Fliker noise
Traps at channel/oxide interface randomly capture/release carriers
Parameterized by Kf and n
Provided by fab (note n ≈ 1)
Currently: Kf of PMOS << Kf of NMOS due to buried channel
To minimize: want large area (high WL)

75. Induced Gate Noise
Fluctuating channel potential couples capacitively into the gate terminal, causing a noise gate current
d is gate noise coefficient
Typically assumed to be 2g
Correlated to drain noise!

76. real
Input impedance
Set to be real and equal to source resistance:

77. Output noise current Noise scaling factor: Where for 0.18 process
c=-j0.55, g=3, d=6, gdo=2gm,
d = 0.32

78. Noise factor
Noise factor scaling coefficient:
Compare:

79. Noise factor scaling coefficient versus Q

80. Example
Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz
From

81. Have We Chosen the Correct Bias Point?
IIP3 is also a function of Q

82. If we choose Vgs=1V Idens = 175 mA/mm From Cgs = 442 fF, W=274mm
Ibias = IdensW = 48 mA, too large!
Solution 1: lower Idens => lower power, lower fT, lower IIP3
Solution 2: lower W => lower power, lower Cgs, higher Q, higher NF

83. Lower current density to 100
Need to verify that IIP3 still OK (once we know Q)

84. Lower current density to 100
We now need to re-plot the Noise Factor scaling coefficient
- Also plot over a wider range of Q

86. Recall
We previously chose Q = 2, let’s now choose Q = 6
- Cuts power dissipation by a factor of 3!
- New value of W is one third the old one

87. Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz
Ibias = IdensW =100mA/mm*91mm=9.1mA
Power = 9.1 * 1.8 = 16.4 mW
Noise factor scaling coeff = 10
Noise factor = 1+ wo/wt * 10
= G/42.8G *10 = 1.42
Noise figure = 10*log(1.42) = 1.52 dB
Cgs=442/3=147fF
Ldeg=Rs/wt=0.19nH
Lg=1/(wo^2Cgs) –Ldeg = 53 nH

88. Other architectures of LNAs
Add output load to achieve voltage gain
In practice, use cascode to boost gain
Added benefit of removing Cgd effect

89. Differential LNA
Value of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits
But: Twice the power as the single-ended version
Requires differential input at the chip

90. LNA Employing Current Re-Use
PMOS is biased using a current mirror
NMOS current adjusted to match the PMOS current
Note: not clear how the matching network is achieving a 50 Ohm match
Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors?

91. Can have differential version
Combining inductive degeneration and current reuse
Current reuse to save power
Larger area due to two degeneration
inductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -
6dBm, Id: 8mA from 2.7V power supply
Can have differential version
F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IEEE JSSC, Vol. 36, No. 10, Oct pp

92. At DC, M1 and M2 are in cascode At AC, M1 and M2 are in cascade
S of M2 is AC shorted
Gm of M1 and M2 are multiplied.
Same biasing current in M1 & M2
LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL® from the February 2004 issue.

93. Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinez
IM3 components in the drain current of the main transistor has the required information of its nonlinearity
Auxiliary circuit is used to tune the magnitude and phase of IM3 components
Addition of main and auxiliary transistor currents results in negligible IM3 components at output
Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinez
IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006

94. MOS in weak inversion has speed problem
MOS transistor in weak inversion acts like bipolar
Bipolar available in TSMC 0.18 technology (not a parasitic BJT)
Why not using that bipolar transistor to improve linearity ?

95. Inter-stage Inductor gain boost
Inter-stage inductor with
parasitic capacitance form
impedance match network between
input stage and cascoded stage
boost gain lower noise figure.
Input match condition will be
affected

96. Folded cascode Low supply voltage Ld reduces or eliminates
Effect of Cgd1
Good fT

97. Design Procedure for Inductive Source Degenerated LNA
Noise factor equations:

98. Targeted Specifications
Frequency 2.4 GHz ISM Band
Noise Figure 1.6 dB
IIP dBm
Voltage gain 20 dB
Power < 10mA from 1.8V

99. Step 1: Know your process
A 0.18um CMOS Process
Process related
tox = 4.1e-9 mm
e = 3.9*(8.85e-12) F/m
m = 3.274e-2 m^2/V.s
Vth = 0.52 V
Noise related
a = gm/gdo
d/g ~ 2
g ~ 3
c = -j0.55

100. Step 2: Obtain design guide plots

101. Insights: gdo increases all the way with current density Iden
gm saturates when Iden larger than 120mA/mm
Velocity saturation, mobility degradation ---- short channel effects
Low gm/current efficiency
High linearity
a deviates from long channel value (1) with large Iden

102. Obtain design guide plots

103. Insights:
fT increases with Vod when Vod is small and saturates after Vod > 0.3V --- short channel effects
Cgs/W increases slowly after Vod > 0.2V
fT begins to degrade when Vod > 0.8V
gm saturates
Cgs increases
Should keep Vod ~0.2 to 0.4 V

104. Obtain design guide plots
knf vs input Q and current density
3-D plot for visual
inspection
2-D plots for
design reference

105. Design trade-offs
For fixed Iden, increasing Q will reduce the size of transistor thus reduce total power ---- noise figure will become larger
For fixed Q, reducing Iden will reduce power, but will increase noise factor
For large Iden, there is an optimal Q for minimum noise factor, but power may be too high

106. Obtain design guide plots
Linearity plots :IIP3 vs. gate overdrive and transistor size

107. Insights: MOS transistor IIP3 only, when embedded into actual circuit:
Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3
IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive is not monotonic
There is a local maxima around 0.1V overdrive

108. Step 4: Estimate fT Small current budget ( < 10mA )
does not allow large gate over drive :
Vod ~ 0.2 V ~ 0.4 V
fT ~ 40 ~ 44 GHz

109. Step 4: Determine Iden, Q and Calculate Device Size
Gm/W~0.4
Select Iden = 70 mA/mm, =>Vod~0.23V

110. If Q = 4, IIP3 will have enough margin:
Estimated IIP3:
IIP3(from curve) – 20log(Q) = 8-12 = -4dBm
Specs require: -8 dBm

111. Q=4 and Iden = 70mA/mm meet the noise factor requirement

112. Gm=0.4*128 ~ 50 mS
fT = gm/(Cgs*2pi) = 48 GHz

113. Step 6: Simulation Verification
Large deviation

115. Comparison between targeted specs and simulation results
Parameter
Target
Simulated
Noise Figure
1.6 dB
0.8 dB
Drain Current
< 10mA
8 mA
Voltage gain
20 dB
21 dB
IIP3
-8 dBm
-6.4 dBm
P1dB
-20dbm
S11
-17 dB
Power supply
1.8 V