1. Front-end for Silicon Photomultiplier (SiPM)
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Front-end for Silicon Photomultiplier (SiPM)

2. SiPM: Silicon photomultiplier
MATRICE DI FOTODIODI A VALANGA POLARIZZATI IN GEIGER MODE
MOLTIPLICAZIONE DEI PORTATORI TRAMITE IL PROCESSO A VALANGA
AMPIEZZA DELl’IMPULSO DI USCITA PROPORZIONALE AL NUMERO DI FOTONI ASSORBITI
24x24 pixels
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3. Cg  10pF, without considering the fringe parasitics
Electrical model of a SiPM
Rq: quenching resistor
(hundreds of kW)
Cd: photodiode capacitance
(few tens of fF)
Cq: parasitic capacitance in parallel to Rq (smaller than Cd)
IAV: current source modelling the total charge delivered by a microcell during the avalanche
 Cg : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with a metal grid.
Example: metal-substrate unit area capacitance 0.03 fF/mm2
metal grid = 35% of the total detector area = 1mm2
 Avalanche time constants much faster than those introduced by the circuit:
IAV can be approximated as a short pulse containing the total amount of charge delivered by the firing microcell Q=DV(Cd+Cq), with DV=VBIAS-VBR
Cg  10pF, without considering the fringe parasitics
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4. a) Transimpedance amplifier
Experimental validation of the model
Two different amplifiers have been used to read-out the FBK-irst SiPM
a) Transimpedance amplifier
BW=80MHz Rs=110W Gain=2.7kW
b) Voltage amplifier
BW=360MHz Rs=50W Gain=140
The model extracted according to the procedure described above has been used in the SPICE simulations
The fitting between simulations and measurements is quite good
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5. Charge sensitive amplifier
Front-end electronics: different approaches - +
SiPM
Vbias CF
VOUT + - RS
SiPM
Vbias
VOUT RS
SiPM
Vbias IS
kIS=IOUT
Charge sensitive amplifier
Voltage amplifier
Current amplifier
The charge Q delivered by the detector is collected on CF
If the maximum DVOUT is 3V and Q is 50pC (about 300 SiPM microcells), CF must be 16.7pF
Perspective limitations in dynamic range, die area, power consumption
A I-V conversion is realized by means of RS
The value of RS affects the gain
and the signal waveform
VOUT must be integrated to extract the charge information: thus a further V-I conversion is needed
RS is the (small) input impedance of the current buffer
The output current can be easily replicated (by means of current mirrors) and further processed (e.g. integrated)
The circuit is inherently fast
Less problems of dynamic range
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6. The CMOS current buffer
0.35mm standard CMOS technology
Common gate configuration (M1)
Feedback applied to increase bandwidth and decrease input resistance (M3, M2)
SiPM bias (and gain) fine tuning possible by varying Vrif
Main simulated specs
Small signal bandwidth: 250MHz  Input resistance: 17W
Total current consumption: 800uA  Linearity dynamic range: about 50pC
Rise time of the output waveform: 400ps  3.3V power supply
Vrif variable in the range 1V÷2V
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7. Experimental setup: blue LED light source
Iout
50Ω
Pulse Generator
Current
Buffer
Voltage
Amplifier
BNC
SiPM
RIV
The circuit has been coupled to a SiPM realized by FBK-Irst 7V
Picture of the setup
Single dark pulse measurement (Vbr=-30.5V; Vbias=-32.5V)
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8. Dark pulse measurements
Charge measurements at Vbias = -32.5V
Comparison with a very fast discrete voltage amplifier front-end, used as a reference:
Average dark pulse charge
Integrated current buffer: 143fC
Discrete voltage amplifier: 142fC
The standard deviation is worse:
sint2sdisc
Blue LED measurements
Comparison with the ref. amplifier :
Average no. of fired microcells
Current buffer: 39
Ref. amplifier: 38.4
Standard deviation
Current buffer: 7.5
Ref. Amplifier: 7.2
Average number of fired microcells as a function of the input pulse width
Charge distribution for a 8.25ns input pulse width (in terms of no. of fired microcells)
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9. Architecture of the analog channel
Variable gain integrator: Gain: 1V/pC  0.33V/pC (2 bits);
f = 200ns;
Output voltage range: 0.3V ÷ 2.7V;
Current mirror scaling factor 10:1
Current discriminator: Current mirror scaling factor 1:1;
Threshold variable from 0 to 40µA (about 50 VBIAS=-31.5V);
Baseline holder : Baseline value Vbl = 300mV
Very slow time constant;
Non-linearities added to prevent baseline shifts at increasing event rates
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10. Typical output waveforms
Experimental setup: LED light source
Lemo
BlueLed
SiPM
Vbias
50Ω Lemo
Pulse Generator
Voltage Buffer
Logic Buffer
Chip
Ch_in
Ch_out
Disc
SiPM A51 ( FBK – IRST )
Blue Led HSMB-C150
Typical output waveforms
(Vbias=31.5V)
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11. Charge measurements (blue LED light source)
Ouput voltage vs pulse width for different gain settings
From the previous characterization measurements we have:
For pulse width = 9ns, n=115 fired microcells 
If Vbias = 31.5 V, the total injected charge is QT= Q µcell(31.5V)*n = 6.9pC
If Vbias = 32.5 V, the total injected charge is QT= Q µcell(32.5V)*n = 17.3pC
Vbias
31.5V
32.5V
QT/(M*Cf)
690mV
1.73V
Vpeak-Vbl
670mV
1.76V
Measurement are in good agreement with the expected results
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12. Design of the 8 channel ASIC: the Peak Detector (PD)
It is based on a P-MOS current mirror as a rectifying element
IBIAS added to improve the speed of operation, especially for small signals
OTA _ +
Integrator output
out
IBIAS
VDISC
Chold=2pF
reset
VDD M1 M2 MR
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13. Design of the 8 channel ASIC: the fast-OR
Fast-OR circuit operating in current mode, to improve the speed of operation
Current buffer to reduce the input impedence
Current discriminator with fixed treshold
Cur_disc M0 M1 M7
trig_0
trig_1
trig_7
Vdd
Vbias
Ibias I0 I1 I2
Ithresh
Cbus
F_or
Ithresh= I2-(I0-I1)
MNBUF
MPBUF
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14. Architecture of the test chip
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config_reg
DAC
Vrif
I_th
MUX_reg
Trig.
reg.
CSA
Curbuf PD
Curdisc
MUX
ADC
Read_out
logic
srq_pad
MUX_sel
F_or
reset_pad
ck_pad
rw_pad
data_pad
gain
ch_0
ch_1
ch_7
EOC
ADC_ck
a_out_0
a_out_1
a_out_7
trig_0
trig_1
trig_7
data
Ext.
bias

15. Design of the 8 channel ASIC: Layout
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16. Read-out procedure for the test chip
Package SMD
A) An event activates the SRQ bus (by default at Hi-Z)
B) FPGA gives a time-stamp to the event and takes control of the SRQ bus during the read-out procedure
C) SRQ, in its active state, is used to “freeze” the content of the trigger registers (no more trigger are accepted)
D) FPGA waits the time needed by the PDs to reach the peak and sends the CLOCK signal to the ASICs
F) The read-out logic starts the A/D conversions and sends the results to FPGA on the DATA_i pad
G) When all the conversions have been completed, FPGA releases the SRQ bus and sends a RESET signal
SRQ
CHIP
DATA
CLOCK
FPGA
DATA_0
RESET
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17. Valore medio del ritardo Valore medio del ritardo
Jitter measurements on fast-OR signal
Misure di jitter in presenza di un solo canale soprasoglia
Misure di jitter in presenza di due canali soprasoglia
Canale colpito
Valore medio del ritardo
Deviazione standard 1
1.77 ns
50 ps 2
1.66 ns
53 ps 3
1.68 ns
49 ps 4
1.69 ns 5
1.74 ns
48 ps 6
1.57 ns 7 8
1.67 ns
Coppia canali
Valore medio del ritardo
Deviazione standard
1-5
1.618 ns
47.26 ps
2-4
1.55 ns
50.5 ps
2-3
48.6 ps
3-4
1.57 ns
49.7 ps
1-4
1.62 ns
49 ps
4-8
1.53 ns
50.3 ps
3-7
50 ps
6-8
1.415 ns
7-8
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18. Design of the 32 channel ASIC: Logic Readout
pd_out_0
Vrif
I_th
ex_ADC
gain
DAC
Vrif
DAC
I_th
pd_out_1
ADC_2
MUX
DEMUX
data
MUX
config_reg
ADC_1
pd_out_31
DEMUX_reg
reset_pad
MUX_reg
rw_pad
MUX_reg
Logic Readout
EOC
ADC/Clock Manager
cK_ADC
coincidence_pad
ck_pad
trig_0
Trig.
reg.
trig_1
SDI_pad
F_or
srq_pad
SDO_pad
trig_31 SS
SPI interface
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