1. CSNSM Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S. Callier, S. Conforti, F. Dulucq, J. Fleury, C. de La Taille, G. Martin- Chassard, L. Raux, N. Seguin-Moreau, V. Tocut + Xiongbo Yan from IHEP Beijing

2. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 2 Microelectronics at in2p3 Large force of microelectronics experienced engineers (~40) Expertise in detectors, chip design and test Experience in designing and building large detectors Common Cadence tools Actions : –Building blocks –Networking –poles

3. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 3 Motivation for poles Continuous increase of chip complexity (SoC, 3D…) Importance of critical mass –Daily contacts and discussions between designers –Sharing of well proven blocks –Cross fertilization of different projects Creation of poles at in2p3 –OMEGA at Orsay –Strasbourg –Dipole Lyon-Clermont

4. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 4 Mission Design of basic building blocks usable by all in2p3 labs for physics experiments Motivations –Target analog technology (0.35µm CMOS and SiGe AMS ) –Optimize ressources and competences within in2p3 –Increase visibility of in2p3 in microelectronics –reduce developpement times First results –2-3 runs /yr financed by in2p3 –Porquerolles workshop –Fruitful exchanges Club building blocks 0.35µm

5. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 5 New club 130nm for tracking and 3D Networking : club 130nm created at VLSI workshop –Target common technology with CERN or other labs : IBM 130nm with CERN, Chartered 130nm (IBM compatible) 3D consortium : CPPM, IPHC, OMEGA, LPNHE –Complementarity –Task sharing –Coordination IN2P3 Recommendation : participate to 3D effort in a coherent, coordinated and funded way.

6. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 6 HARDROC Orsay Micro-Electronics Groups Associated A strong team of 10 ASIC designers… –= 20% of in2p3 designers –= 60% of department research engineers –A team with critical mass : pole created in 2007 = OMEGA –Expertise in low noise, low power high level of integration ASICs –2 designers/ project –2 projects/designer –Regular design meetings …Within an electronics departmt of 50 –Support for tests, mesaurements, PCBs… A steady production –A strong on-going R&D –Building blocks SiGe 0.35µm SKIROC MAROC 2 SPIROC ASPIC

7. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 7 Orsay micro-electronics team 8 research engineers (1 IR0, 2 IR1, 5 IR2) 1 CDD IR2 EUDET 1 phD student 1 visitor from China IHEP Beijing

8. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 8 Recent chips Several chips developped for ATLAS LAr, OPERA, LHCb, CALICE in BiCMOS 0.8µm and installed on experiments Turn to Silicon Germanium 0.35 µm SiGe BiCMOS technology in 2005 Readout for MaPMT and ILC calorimeters Very high level of integration : System on Chip (SoC) Parallel activity of building blocks SKIROC MAROC 2 HARDROCSPIROCASPIC

9. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 9 MAROC : 64 ch MAPMT chip for ATLAS lumi Complete front-end chip for 64 channels multi-anode photomultipliers –Auto-trigger on 1/3 p.e. at 10 MHz, 12 bit charge output –SiGe 0.35 µm, 12 mm2, Pd = 350mW PMF Hold signal PM 64 channels Photons Variable Gain Preamp. Variable Slow Shaper 20-100 ns Bipolar Fast Shaper Unipolar Fast Shaper Gain correction 64*6bits 3 discris thresholds (3*12 bits) Multiplexed Analog charge output LUCID S&H 3 DACs 12 bits 80 MHz encoder 64 Wilkinson 12 bit ADC 64 trigger outputs (to FPGA) Multiplexed Digital charge output 64 inputs S&H

10. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 10 Active board pictures MAROC side Lattice side 64 ch PMT MAROC2 chip bounded at CERN

11. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 11 MAROC Efficiency curves

12. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 12 ILC Challenges for electronics Requirements for electronics –Large dynamic range (15 bits) –Auto-trigger on ½ MIP –On chip zero suppress –Front-end embedded in detector –Ultra-low power : («25µW/ch ) –10 8 channels –Compactness « Tracker electronics with calorimetric performance » No chip = no detector !! ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/chILC : 25µW/ch W layer ASIC Ultra-low POWER is the KEY issue Si wafers

13. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 13 The front-end ASICs : the ROC chips SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 07 HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Technological prototypes : full scale modules (~2m) EUDET EU funding (06-09) ECAL, AHCAL, DHCAL B=5T

14. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 14 DHCAL chip : HaRDROC Hadronic Rpc Detector Read Out Chip (Sept 06) –64 inputs, preamp + shaper+ 2 discris + memory + Full power pulsing –Compatible with 1st and 2nd generation DAQ : token ring readout of up to 100 chips –First test of 2 nd generation DAQ –First test detector integration Collaboration with IPNL/LLR/Madrid/Protvino –1m 3 scalable detector –Production of 5000 chips in 2009

15. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 15 HaRDROC architecture Variable gain (6bits) current preamps (50ohm input) One multiplexed analog output (12bit) Auto-trigger on ½ MIP Store all channels and BCID for every hit. Depth = 128 bits Data format : 128(depth)*[2bit*64ch +24bit(BCID)+8bit(He ader)] = 20kbits Power dissipation : 1.5 mW/ch (unpulsed)- > 15µW with 1% cycle Large flexibility via >500 slow control settings

16. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 16 30 fC 10 fC Pedestal Dac unit Channel number S-curves of 64 channels 10 bit DAC for threshold Noise ~ 1 UDAC (2mV) Pedestal dispersion : 0.4 UDAC rms Gain dispersion 3% rms Crosstalk : < 2% 50% trigger versus channel number

17. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 17 SKIROC for W-Si ECAL Silicon Kalorimeter Integrated Read Out Chip (Nov 06) –36 channels with 15 bits Preamp + bi-gain shaper + autotrigger + analog memory + Wilkinson ADC –Digital part outside in a FPGA for lack of time and increased flexibility –Technology SiGe 0.35µm AMS. Chip received may 07 1 MIP in SKIROC

18. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 18 12 bit Wilkinson ADC performance Noise in low gain shaper rms = 0.9UADC (330µV) MIP =3 UADC 1050 1080 Noise in high gain shaper rms = 4UADC (1.4mV) MIP=30UADC Pedestal value vs Channel number Noise vs Channel number 4 5

19. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 19 Front-end board for ECAL PCB – FRONT PCB – BACK An ASU (Active Sensor Unit) VFE ASIC bonded in a PCB ASIC buried in the PCB ASU stitching : zero thickness connection No component  All features embedded in ASIC

20. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 20 Second generation chip for SiPM SPIROC : Silicon Photomul. Integrated Readout Chip –36 channels –Charge measurement –Time measurement –Autotrigger on MIP or spe –Sparsified readout compatible with EUDET 2 nd generation DAQ –Chips daisy-chained –Pulsed power -> 25 µW/ch Fabricated in SiGe AMS 0.35 µm –Submitted in june 07 –Chip area : 30 mm2

21. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 21 SPIROC main features Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment Energy measurement : 14 bits –2 gains (1-10) + 12 bit ADC 1 pe  2000 pe –Variable shaping time from 50ns to 100ns –pe/noise ratio : 11 Auto-trigger on 1/3 pe (50fC) –pe/noise ratio on trigger channel : 24 –Fast shaper : ~10ns –Auto-Trigger on ½ pe Time measurement : –12-bit Bunch Crossing ID –12 bit TDC step~100 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 10 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout

22. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 22 SPIROC : One channel schematic IN test

23. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 23 DAQ ASIC Chip ID register 8 bits gain Trigger discri Output Wilkinson ADC Discri output gain Trigger discri Output Wilkinson ADC Discri output..… OR36 EndRamp (Discri ADC Wilkinson) 36 TM (Discri trigger) ValGain (low gain or high Gain) ExtSigmaTM (OR36) Channel 1 Channel 0 ValDimGray 12 bits … Acquisition readout Conversion ADC + Ecriture RAM RAM FlagTDC ValDimGray 12 8 ChipID Hit channel register 16 x 36 x 1 bits TDC ramp StartRampTDC BCID 16 x 8 bits ADC ramp Startrampb (wilkinson ramp) 16 ValidHoldAnalogb RazRangN 16 ReadMesureb Rstb Clk40MHz SlowClock StartAcqt StartConvDAQb StartReadOut NoTrig RamFull TransmitOn OutSerie EndReadOut Chipsat

24. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 24 SPIROC performance Good analog performance –Single photo-electron/noise = 8 –Auto-trigger with good uniformity –Complex chip : many more measurements needed bug in the ADC necessitates an iteration

25. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 25 Joël PouthasIPN Orsay “PMm2” (2006 – 2009), funded by the ANR : LAL, IPNO, LAPP and Photonis Replace large PMTs (20”) by groups of smaller ones (12”) – central 16ch ASIC (PaRISROC) –12 bit charge + 12 bit time –water-tight, common High Voltage –Only one wire out (DATA + VCC) –Target low cost –Reuse many parts from MAROC & SPIROC Application : large water Cerenkov neutrino –1ns time resolution –High granularity –scalability PMm 2 : large photodection area

26. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 26 Based on a complete 16 channels read out chip with dedicated for Photomultiplier array (PARISROC) Measurement of Charge and time PArISROC specifications

27. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 27 ASIC Architecture Channel 16 Channel 1 16 charge inputs Variable Gain Amplifier (1-8) Gain Correction (8bits) CRRC2 Slow Shaper (50, 100, 200 ns) Differential Fast Shaper (15ns) Discri 12 bits ADC Track & hold Threshold 1 digital charge output variable delay 1 ext. Common Hold OR 16 Trigger outputs 24 bits counter 10MHz 24bits absolute time measurement Bandgap Vref SSH Vref FSH Vref SSH 1 OR output Internal read DAC 10 bits OR  new blocks  slow control signal DAC 4 bits Threshold (4bits/ch)

28. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 28 3D technology Increasing integration density, mixing technologies Wafer thinning to <50 µm Minimization of interconnects Large industrial demand –Processors, image sensors… ©A. Klumpp (IZM)

29. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 29 Major Markets for 3D [R. Yarema FNAL] Pixel arrays for imaging Pixel arrays with sensors and readout are well suited to 3D integration since signal processing can be placed close to the sensor. Current 2D approaches cannot handle the data rate needed for high speed imaging. Memory All major memory manufactures are working on 3D memory stacks. Significant cost reductions can be expected for large memory devices. The cost of 3D can be significantly less than going to a deeper technology node. Microprocessors A major bottleneck is access time between CPU and the memory. Memory caches are used as an interface but the area required is significant. Initial applications for 3D will use Logic to Memory, and Logic to Logic stacking. (Samsung)

30. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 30 3D consortium Collaboration between IN2P3, INFN and FNAL –SLHC, ILC and SuperB applications Chartered 0.13µm and Tezzaron process chosen –« IBM compatible » process –Via first : 1-2 µm vias –Assembled by Tezzaron –Run coordinated by FNAL

31. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 31 8 inch wafers Large reticule – 24 mm x 32 mm Features –Deep N-well –MiM capacitors – 1 fF/um 2 –Single poly –8 levels of metal available –Zero Vt (Native NMOS) available –A variety of transistor options with multiple threshold voltages can be used simultaneously Nominal Low voltage High performance Low power Eight inches Chartered 0.13 um Process

32. Orsay, 19 jan 2009C. de La Taille - microelectronics at OMEGA-LAL 32 Tezzaron 3D Process Complete back end of line (BEOL) processing by adding Cu metal layers and top Cu metal (0.8 um) 6 um Cu

33. Orsay, 19 jan 2009C. de La Taille - microelectronics at OMEGA-LAL 33 Tezzaron 3D Process Flip 2 nd wafer on top of first wafer. Bond second wafer to first wafer using Cu-Cu thermo-compression bond. Example: bonding identical wafers CuCu bond 12um Thin second wafer to about 12um to expose super via. Add metallization to back of 2 nd wafer for bump bond or wire bond. OR Add Cu to back of 2 nd wafer to bond 2 nd wafer to 3 rd wafer Cu for wafer bond to 3 rd layer

34. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 34 Reticule E2

35. Orsay, 19 jan 2009C. de La Taille - microelectronics at OMEGA-LALTWEPP-08 35 Three Tier Arrangement for VIP1 Pixel : FNAL 22 um

36. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 36 3D for ATLAS CPPM : –move FEI4 from IBM 0.13µm to FEC4 Chartered 0.13µm (2D) –Target Mosis run 23/1/09 –Fold FEC4 2D chip into FETC4 chip 3D (CPPM, Bonn,LBL), keep analog part in analog tier and put a simple register in digital tier LAL : –Study smaller pixels (50x50µm instead of 50x250) –Match Munich new ATLAS pixel prototype –Target 10 µW/ch => 400 mW/cm 2 –Design analog tier with low noise low power preamp including shaping + threshold DAC –Discriminator in digital tier + dynamic memory –Study digital coupling to analog tier with discri in digital tier –Study variants of blocks for FEI4 (preamp, discri,DAC, local storage…)

37. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 37 Next steps Omega will participate to march08 run Aim at studying 3D design for low power, small area pixels Will submit a chip with –One analog tier of low power, low noise preamp, low offset discriminator for 50x50µ pixels –One digital tier of local memory, sparsification and readout Collaboration with –ATLAS pixel group –FNAL CMS SLHC (R. Yarema) –INFN SuperB (V. Re) Sensor layer Pad 50  m Pad Analogue AOP Digital tier

38. Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 38 Conclusion MAROC, HaRDROC, SKIROC, SPIROC… –4 complex ASICs prototyped in 2007 : 2 nd generation chips –SoC : System on chip (ADC, TDC, DAQ…) –Production in 2009 in a dedicated run ILC main customer –Many external requests –Long and difficult measurements… Coming up : 3D –CMOS 130nm –Basic analog tier for 3D integration in collaboration with CPPM Marseille aimed at 50x50µm pixels simple readout.