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CS 140 Lecture 7 Professor CK Cheng 10/17/02. Combinational Logic  Complete set of gates  Other types of gates 1)XOR 2)NAND / NOR 3)Block Diagram Transfers.

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Presentation on theme: "CS 140 Lecture 7 Professor CK Cheng 10/17/02. Combinational Logic  Complete set of gates  Other types of gates 1)XOR 2)NAND / NOR 3)Block Diagram Transfers."— Presentation transcript:

1 CS 140 Lecture 7 Professor CK Cheng 10/17/02

2 Combinational Logic  Complete set of gates  Other types of gates 1)XOR 2)NAND / NOR 3)Block Diagram Transfers

3 Complete Set of Gates (Universal Set) A set of gates such that every switching function can be implemented with gates in this set. Ex: {AND, OR, NOT} {AND, NOT} OR can be implemented with AND & NOT gates a+b = (a’b’)’ {OR, NOT} AND can be implemented with OR & NOT gates ab = (a’+b’)’ {AND, OR} This is not universal.

4 {NAND, NOR} {NOR} {XOR, AND} X 1 = X*1’ + X*1 = X’ if constant “1” is available. 1

5 Other types of gates (a)Commutative X Y = Y X (b)Associative (X Y) Z = X (Y Z) (c)1 X = X’ 0 X = 0X’ + 0’X = X (d)X X = 0, X X’ = 1 1) XOR X Y = XY’ + X’Y XOR X Y

6 e) if ab = 0 then a b = a + b Proof: If ab = 0 then a = a (b+b’) = ab+ab’ = ba’ b = b (a + a’) = ba + ba’ = ba’ a+b = ab’ + a’b = a b f) X XY’ X’Y (X + Y) X = ?? To answer, we apply Shannon’s Expansion

7 Shannon’s Expansion (for switching functions) f (x,Y) = x * f (1, Y) + x’ * f (0, Y) If x = 1, f (x,Y) = f (1, Y) : 1*f (1, Y) + 1’*f(0,Y) = f (1, Y) If x = 0, f(x,Y) = f (0, Y) : 0*f (1, Y) + 0’*f(0,Y) = f(0, Y)

8 Back to our problem… X XY’ X’Y (X + Y) X = ?  X (XY’) (X’Y) (X + Y) X = f (X, Y) If X = 1, f (1, Y) = 1 Y’ 0 1 1 = Y If X = 0, f (0, Y) = 0 0 Y Y 0 = 0 Thus, f (X, Y) = XY

9 2) NAND, NOR gates NAND, NOR gates are not associative Let a | b = (ab)’ (a | b) | c = a | (b | c)

10 3) Block Diagram Transformation a) Reduce # of inputs.  

11 b. DeMorgan’s Law  (a+b)’ = a’b’  (ab)’ = a’+b’

12 c. Sum of Products (Using only NAND gates)   Sum of Products (Using only NOR gates)  

13 d. Product of Sums (NOR gates only) 

14 Part II. Sequential Networks (Ch. 7.1-7.5) Memory / Timesteps Clock Flip flops Specification Implementation


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