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Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

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Presentation on theme: "Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis."— Presentation transcript:

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2 Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis

3 CMOS NAND Gates Use 2n transistors for n-input gate

4 CMOS NAND -- switch model

5 CMOS NAND -- more inputs (3)

6 Inherent inversion. Non-inverting buffer:

7 2-input AND gate:

8 CMOS NOR Gates Like NAND -- 2n transistors for n-input gate

9 NAND vs. NOR For a given silicon area, PMOS transistors are “weaker” than NMOS transistors. NANDNOR Result: NAND gates are preferred in CMOS.

10 Boolean algebra a.k.a. “switching algebra” –deals with boolean values -- 0, 1 Positive-logic convention –analog voltages LOW, HIGH --> 0, 1 Negative logic -- seldom used Signal values denoted by variables (X, Y, FRED, etc.)

11 Boolean operators Complement:X (opposite of X) AND:X  Y OR:X + Y Axiomatic definition: A1-A5, A1-A5 binary operators, described functionally by truth table.

12 More definitions Literal: a variable or its complement –X, X, FRED, CS_L Expression: literals combined by AND, OR, parentheses, complementation –X+Y –P  Q  R –A + B  C –((FRED  Z) + CS_L  A  B  C + Q5)  RESET Equation: Variable = expression –P = ((FRED  Z) + CS_L  A  B  C + Q5)  RESET

13 Logic symbols

14 Theorems Proofs by perfect induction

15 More Theorems N.B. T8, T10, T11

16 Duality Swap 0 & 1, AND & OR –Result: Theorems still true Why? –Each axiom (A1-A5) has a dual (A1-A5  Counterexample: X + X  Y = X (T9) X  X + Y = X (dual) X + Y = X (T3) ???????????? X + (X  Y) = X (T9) X  (X + Y) = X (dual) (X  X) + (X  Y) = X (T8) X + (X  Y) = X (T3) parentheses, operator precedence!

17 N-variable Theorems Prove using finite induction Most important: DeMorgan theorems

18 DeMorgan Symbol Equivalence

19 Likewise for OR (be sure to check errata!)

20 DeMorgan Symbols

21 Even more definitions (Sec. 4.1.6) Product term Sum-of-products expression Sum term Product-of-sums expression Normal term Minterm (n variables) Maxterm (n variables)

22 Truth table vs. minterms & maxterms

23 Combinational analysis

24 Signal expressions Multiply out: F = ((X + Y)  Z) + (X  Y  Z) = (X  Z) + (Y  Z) + (X  Y  Z)

25 New circuit, same function

26 “Add out” logic function Circuit:

27 Shortcut: Symbol substitution

28 Different circuit, same function

29 Another example

30 Short Review of Exor Logic A  A = 0 A  A’ = 1 A  1=A’ A’  1=A A  0=A A  B= B  A A B = B A A(B  C) = AB  AC A+B = A  B  AB A+B = A  B when AB = 0 A  (B  C) = (A  B)  C (A B) C = A (B C) A+B = A  B  AB = A  B(1  A) = A  BA’ These rules are sufficient to minimize Exclusive Sum of Product expression for small number of variables We will use these rules in the class for all kinds of reversible, quantum, optical, etc. logic. Try to remember them or put them to your “creepsheet”.

31 Challenge Problems for ambitious students Problem 1.Problem 1. Express function AB+CD+A’C using only EXORs and AND gates Problem 2Problem 2. Prove that A+B = A  B  AB Problem 3Problem 3. Prove that A+B = A  B when AB = 0 Problem 4. Given are three functions of three inputs: A = NOT(a), B = NOT(b), C = NOT(c). You have only two inverters. You can have an arbitrary large set of two-input AND and OR gates. Realize these three functions with the gates that you have at your disposal. You cannot use other gates. You can use only two inverters. Draw the schematic of the solution


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