1. Input-Output Problems L1 Prof. Sin-Min Lee Department of Mathematics and Computer Science

12. Synchronous -----all state bits change at same time on a common clock.

14. Buses The buses that connect the three main parts of a computer system are called the control bus, the data bus and the address bus.

18. A processor has a 24 bit address line and 8 bit data line bus structure. a.What is the maximum number of rows (cells) it can address? Answer: 2 **24 = 16777216 rows or cells (1 byte) can be addressed independently b.If the processor is word addressable only (one word consisting of 2 bytes) what is the addressable space) Answer: 16777216 words are addressable but only one byte can be accessed because of the byte wide data bus.

23. Sample Peripherals - I/O Transfer Rate The data transfer rate of the three peripherals mentioned are as follow: –Keyboard 10 bytes per second –Hard drive 20 MB per second –CRT75 MB per second

24. I/O Interfaces CPU & memory need special communication links to resolve the differences in properties with peripherals 1.Peripherals are often electromechanical devices whose manner of operation is different from that of the CPU and memory, which are electronic devices. Therefore, a conversion of signal values may be requires

25. I/O Interfaces 2.The data transfer rate of peripherals is usually different from the clock rate of the CPU. Consequently, a synchronization mechanism may be needed 3.Data code and formats in peripherals differ from the word format in the CPU and memory 4.The operating modes of peripherals differ from each other, and each must be controlled in a way that does not disturb the operation of other peripherals connected to the CPU

27. I/O Interfaces - Bus and Interface Unit

28. Three ways that external computer buses communicate with memory and I/O –Memory-mapped I/O –Isolated I/O configuration –Data channel

29. I/O Interfaces - Bus and Interface Unit Memory-mapped I/O –Use common data, address, control bus for memory and I/O Isolated I/O configuration –Use common data, address bus but different control bus Data channel –Use two independent sets of data, address, and control bus

30. I/O Interfaces - Bus and Interface Unit Data channel method is possible with computer with I/O processor in addition to CPU Memory communicate with CPU and I/O processor through common memory bus

31. Example of I/O Interface

32. I/O Interfaces - Example of I/O Interface –Receives control information from CPU –A bit in this register determine the operating mode of the device Control register –Contains bit to indicate status condition and record any error during transfer Status register –Communicate with CPU via bidirectional bus Interface registers

33. Data bus select the interface units through chip select input (CS) and two register select (RS0) and (RS1) CPU and I/O devices are likely to have different clock rate that are not synchronized A control signal is needed to –Indicate time the data is being transmitted –Indicate the window of time when the address is valid

34. I/O Interfaces - Example of I/O Interface Two methods to perform this timing between CPU and devices –Strobing –Handshaking

44. Interrupt

46. The memory address in the above table (column 3) is the location of the handler routine that will be executed as a result of the interrupt. Location of table hardwired in machine, initialized by OS