1. CS152 Lec11.1 CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design (Continued)

2. CS152 Lec11.2 The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topics: Microprogramed control Administrivia Microprogram it yourself Exceptions Control Datapath Memory Processor Input Output

3. CS152 Lec11.3 Controller Design °The state digrams that arise define the controller for an instruction set processor are highly structured °Use this structure to construct a simple “microsequencer” °Control reduces to programming this very simple device  microprogramming sequencer control datapath control micro-PC sequencer microinstruction

4. CS152 Lec11.4 Multicycle Datapath PC Next PC Operand Fetch Instruction Fetch nPC_sel IR Reg File Ext ALU Reg. File Mem Acces s Data Mem Result Store RegDst RegWr MemWr MemRd S M MemToReg Equal ALUctr ALUSrc ExtOp A B E

5. CS152 Lec11.5 State Diagram of Controller IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ PC <= Next(PC) SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 00111011 1100 Execute Memory Write-back

6. CS152 Lec11.6 Using a Jump Counter IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ PC <= Next(PC) SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 00111011 1100 inc load zero inc Execute Memory Write-back

7. CS152 Lec11.7 Example: Jump-Counter op-code Map ROM Counter zero inc load 0000 i i+1 i None of above: Do nothing (for wait states)

8. CS152 Lec11.8 Sequencer °Sequencer-based control unit Called “microPC” or “µPC” vs. state register Control ValueEffect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 Dispatch ROM: Opcode microPC 1 µAddress Select Logic Adder Dispatch ROM Mux 0 012 OpcodeDispatch State R-type0000000100 BEQ0001000011 ori0011010110 LW1000111000 SW1010111011 Microprogram

9. CS152 Lec11.9 Microprogramming (Maurice Wilkes) °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

10. CS152 Lec11.10 “Macro and micro - instruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA...... User program plus Data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) one of these is mapped into one of these

11. CS152 Lec11.11 Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points (remember ALU?) branch:µseq-opµadd execute:ALU-opA,B,R memory:mem-opS, D µseq µaddr A-mux B-mux bus enables register enables Horizontal Vertical

12. CS152 Lec11.12 Extreme Horizontal input select N3N2 N1N0... 13 Incr PC ALU control 1 bit for each loadable register enbMAR enbAC... Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time. Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction

13. CS152 Lec11.13 More Vertical Format src dst DECDEC DECDEC other control fields next statesinputs MUX Multiformat Microcode: 13 6 1333 0condnext address 1dstsrcalu DECDEC DECDEC Branch Jump Register Xfer Operation

14. CS152 Lec11.14 Hybrid Control Not all critical control information is derived from control logic E.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. Register File RS1DECRS1DEC RS2DECRS2DEC RDDECRDDEC op rs1 rs2rdIR to control enable signals from control

15. CS152 Lec11.15 Summary: Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal + more control over the potential parallelism of operations in the datapath - uses up lots of control store Vertical + easier to program, not very different from programming a RISC machine in assembly language - extra level of decoding may slow the machine down

16. CS152 Lec11.16 Microprogramming a multicycle processor °1) Choose datapath and sequencer architecture °2) Assign states and sequence of each (multicycle) instruction (i.e. define the controller FSM) °2) Choose microinstruction format (minimum bits to describe all allowable functions of sequencer and datapath) °3) Map instructions into microinstruction sequences

17. CS152 Lec11.17 Sequencer °Sequencer-based control unit Called “microPC” or “µPC” vs. state register Control ValueEffect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 Dispatch ROM: Opcode microPC 1 µAddress Select Logic Adder Dispatch ROM Mux 0 012 OpcodeDispatch State R-type0000000100 BEQ0001000011 ori0011010110 LW1000111000 SW1010111011 Microprogram

18. CS152 Lec11.18 Datapath – single memory, single regfile °Miminizes Hardware: 1 memory, 1 adder Ideal Memory WrAdr Din RAdr 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 01 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A

19. CS152 Lec11.19 Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 R-type ALUout <= A fun B R[rd] <= ALUout ALUout <= A or ZX R[rt] <= ALUout ORi ALUout <= A + SX R[rt] <= M M <= MEM[ALUout] LW ALUout <= A + SX MEM[ALUout] <= B SW “instruction fetch” “decode” Execute Memory Write-back 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 BEQ 0010 0011 If A = B then PC <= ALUout ALUout <= PC +SX Q: What can we do in state 0001?

20. CS152 Lec11.20 Finite State Machine (FSM) Spec (improved) IR <= MEM[PC] PC <= PC + 4 R-type ALUout <= A fun B R[rd] <= ALUout ALUout <= A or ZX R[rt] <= ALUout ORi ALUout <= A + SX R[rt] <= M M <= MEM[ALUout] LW ALUout <= A + SX MEM[ALUout] <= B SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 BEQ 0010 If A = B then PC <= ALUout ALUout <= PC +SX Execute Memory Write-back

21. CS152 Lec11.21 Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 5) To minimize the width, encode operations that will never be used at the same time

22. CS152 Lec11.22 1) Start with list of control signals Signal nameEffect when deassertedEffect when asserted ALUSelA1st ALU operand = PC1st ALU operand = Reg[rs] RegWrNoneReg. is written MemtoRegReg. write data input = ALUReg. write data input = memory RegDstReg. dest. no. = rtReg. dest. no. = rd MemRdNoneMemory at address is read, MemWrNoneMemory at address is written IorDMemory address = PCMemory address = S IRWrNoneIR <= Memory PCWrNonePC <= PCSource PCWrCond NoneIF ALUzero then PC <= PCSource PCSrc PCSource = ALU PCSource = ALUout ExtOpZero ExtendedSign Extended Single Bit Control Signal nameValueEffect ALUOp00ALU adds 01ALU subtracts 10ALU does function code 11ALU does logical OR ALUSelB002nd ALU input = 4 012nd ALU input = Reg[rt] 102nd ALU input = extended,shift left 2 112nd ALU input = extended Multiple Bit Control

23. CS152 Lec11.23 2) Group into fields of unrelated signals °Miminizes Hardware: 1 memory, 1 adder Ideal Memory WrAdr Din RAdr 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 01 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A ALU SRC1 SRC2 MemRd PCWrite

24. CS152 Lec11.24 2,3 & 4 ) Group into fields, order and assign names Field NameValues for FieldFunction of Field with Specific Value ALUAddALU adds Subt. ALU subtracts FuncALU does function code OrALU does logical OR SRC1PC1st ALU input <= PC rs1st ALU input <= Reg[rs] SRC242nd ALU input <= 4 Extend2nd ALU input <= sign ext. IR[15-0] Extend02nd ALU input <= zero ext. IR[15-0] Extshft2nd ALU input <= sign ex., sl IR[15-0] rt2nd ALU input <= Reg[rt] dest(ination)rd ALUReg[rd] <= ALUout rt ALUReg[rt] <= ALUout rt Mem Reg[rt] <= Mem Mem(ory)Read PCRead memory using PC Read ALURead memory using ALUout for addr Write ALUWrite memory using ALUout for addr MemregIRIR <= Mem PCwritePCwrPC <= PCSource PCSrc IF Zero then PCSource <= ALUout else ALU PCWrCond I F Zero then PC <= PCSource Seq(uencing)SeqGo to sequential µinstruction FetchGo to the first microinstruction DispatchDispatch using ROM. ALUSRC 1 SRC 2 DestMemMemregPCwriteSeq

25. CS152 Lec11.25 5) Encode each field Field NameWidthControl Signals Set wide narrow ALU 42ALUOp SRC121ALUSelA SRC253ALUSelB, ExtOp Dest32RegWrite, MemtoReg, RegDst Mem32MemRd, MemWre, IorD Memreg11IRWrite PCWrite31PCWr, PCSrc, PCWrCond Seq32AddrCtl Total width2414bits

26. CS152 Lec11.26 5) Encode each field (cont.) CodeNameRegWriteMemToRegRegDest 00---0XX 01rd ALU101 10rt ALU100 11rt MEM110 CodeNameALUSelBExtOp 000---XX 001400X 010rt01X 011ExtShft101 100Extend111 111Extend0110 Dest: SRC2:

27. CS152 Lec11.27 Finally – Do the microprogram…. Label ALU SRC1SRC2Dest.Memory MemReg. PCWrite Seq Fetch:AddPC4Read PCIRPCwrSeq AddPCExtshftDispatch Rtype:FuncrsrtSeq rd ALUFetch Ori:Orrs Extend0 Seq rt ALUFetch Lw:AddrsExtend Seq Read ALU Seq rt MEM Fetch Sw:AddrsExtendSeq Write ALUFetch Beq:Subt.rsrt PCWrCond.Fetch 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 0010

28. CS152 Lec11.28 Microprogramming Pros and Cons °Ease of design °Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field °Can implement very powerful instruction sets (just more control memory) °Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. °Compatibility Many organizations, same instruction set °Costly to implement °Slow

29. CS152 Lec11.29 Adding a more complex memory model PC Instruction Memory Inst. Reg addr data IR_en InstMem_rd IM_wait Add a wait flag of indeterminate length – IM_wait (due to caching)

30. CS152 Lec11.30 Controller handles non-ideal memory IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B BEQ PC <= Next(PC) SW “instruction fetch” “decode / operand fetch” Execute Memory Write-back ~IMwait IMwait ~waitwait PC <= PC + 4 ~wait wait

31. CS152 Lec11.31 Really Simple Time-State Control instruction fetch decode Execute Memory IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B BEQ PC <= Next(PC) SW ~IMwait IMwait wait PC <= PC + 4 wait write-back

32. CS152 Lec11.32 Time-state Control Path °Local decode and control at each stage Exec Reg. File Mem Acces s Data Mem ABSM Reg File Equal PC Next PC IR Inst. Mem Valid IRex Dcd Ctrl IRmem Ex Ctrl IRwb Mem Ctrl WB Ctrl

33. CS152 Lec11.33 Overview of Control °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation PLAROM Technique “hardwired control”“microprogrammed control”

34. CS152 Lec11.34 Summary °Specialize state-diagrams easily captured by microsequencer simple increment & “branch” fields datapath control fields °Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) °Steps: identify control signals, group them, develop “mini language”, then microprogram °Control design reduces to Microprogramming Arbitrarily complicated instructions possible

35. CS152 Lec11.35 Summary: Microprogramming one inspiration for RISC °If simple instruction could execute at very high clock rate… °If you could even write compilers to produce microinstructions… °If most programs use simple instructions and addressing modes… °If microcode is kept in RAM instead of ROM so as to fix bugs … °If same memory used for control memory could be used instead as cache for “macroinstructions”… °Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine?