1. ECE 232 L16.Microprog.1 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers ECE 232 Hardware Organization and Design Lecture 16 Microprogrammed Control Maciej Ciesielski www.ecs.umass.edu/ece/labs/vlsicad/ece232/spr2002/index_232.html

2. ECE 232 L16.Microprog.2 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Outline °Review FSM-based control Structured control logic °Microprogramming Basic concept – sequencing control Designing a microinstruction code Variations: horizontal vs. vertical microprogram °Overview of control State machine vs. microprogram

3. ECE 232 L16.Microprog.3 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topics: microprogrammed control Control Datapath Memory Processor Input Output

4. ECE 232 L16.Microprog.4 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Controller Design °The state diagrams that define the controller for an instruction set processor are highly structured °Use this structure to construct a simple “microsequencer” °Control reduces to programming this very simple device microprogramming sequencer control datapath control micro-PC sequencer microinstruction

5. ECE 232 L16.Microprog.5 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Example: Jump-Counter op-code Map ROM Counter zero inc load 0000 i i+1 i Zero Increment Load

6. ECE 232 L16.Microprog.6 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Using a Jump Counter IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ & Equal BEQ & ~Equal PC <= PC + 4 PC <= PC + SX || 00 SW “instruction fetch” “decode” Execute Memory Write-back 0000 0001 0100 0101 0110 0111 1000 1001 1010 0011 0010 1011 1100 inc loadinc zero inc

7. ECE 232 L16.Microprog.7 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Our Microsequencer op-code Map ROM Micro-PC Z I L Datapath control taken (from IR) Z = zero I = increment L = load (branch)

8. ECE 232 L16.Microprog.8 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Microprogram Control Specification 0000?inc1 00010load 00011inc 0010xzero1 1 0011xzero1 0 0100xinc0 1 fun 1 0101xzero1 00 1 1 0110xinc0 0 or 1 0111xzero1 00 1 0 1000xinc1 0 add 1 1001xinc1 0 0 1010 xzero1 01 1 0 1011xinc1 0 add 1 1100xzero 1 00 1 µPC TakenNext IRPCOpsExecMemWrite-Back en selA B Ex Sr ALU S R W MM-R Wr Dst R: ORi: LW: SW: BEQ

9. ECE 232 L16.Microprog.9 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers How Effectively are we utilizing our hardware? °Example: memory is used twice, at different times Avg. mem access per inst = 1 + Flw + Fsw ~ 1.3 if CPI is 4.8, Instr-mem utilization = 1/4.8, Data-mem = 0.3/4.8 °We could reduce HW without hurting performance extra control IR <- Mem[PC] A <- R[rs]; B<– R[rt] S <– A + B R[rd] <– S; PC <– PC+4; S <– A + SX M <– Mem[S] R[rd] <– M; PC <– PC+4; S <– A or ZX R[rt] <– S; PC <– PC+4; S <– A + SX Mem[S] <- B PC <– PC+4; PC < PC+4;PC < PC+SX;

10. ECE 232 L16.Microprog.10 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers “Princeton” Organization (von Neumann) °Single memory for instruction and data access memory utilization -> 1.3/4.8 °In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle Reg File A B A- Bus B Bus IR S W-Bus PCPC next PC ZXSX Mem

11. ECE 232 L16.Microprog.11 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Alternative datapath (book): Multiple Cycle Datapath °Minimizes hardware: 1 memory, 1 adder

12. ECE 232 L16.Microprog.12 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Our Controller FSM Spec “instruction fetch” “decode” Write-back IR <= MEM[PC] PC <= PC + 4 0000 A <= R[rs] B <= R[rt] 0001 R-type S <= A fun B R[rd] <= S S <= A op ZX R[rt] <= S ORi S <= A + SX R[rt] <= M M <= MEM[S] LW S <= A + SX MEM[S] <= B SW Execute Memory 0100 0101 0110 0111 1000 1001 1010 1011 1100 ~EqualEqual BEQ PC <= PC + SX || 00 0010 0011 S <= A - B

13. ECE 232 L16.Microprog.13 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Microprogramming °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming : A particular strategy for implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture : Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

14. ECE 232 L16.Microprog.14 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers FSM-based Control Unit to Multi-cycle Datapath Next state Inputs Outputs Combinational logic unit Inputs from Instruction Register OPcode field State Reg OP PS NS

15. ECE 232 L16.Microprog.15 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Sequencer-based Control Unit Multi-cycle Datapath Types of “branching” Set state to 0 Dispatch (state 1) Use incremented state number Opcode State Reg Inputs Outputs Control Logic 1 Address Select Logic Adder

16. ECE 232 L16.Microprog.16 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers “Macroinstruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA...... User program plus data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) each of these is mapped into one of these

17. ECE 232 L16.Microprog.17 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points branch:µseq-opµadd execute:ALU-opA,B,R memory:mem-opS, D µseq µaddr A-mux B-mux bus enables register enables Horizontal Vertical

18. ECE 232 L16.Microprog.18 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Extreme Horizontal input select N3N2 N1N0... 13 Incr PC ALU control 1 bit for each loadable register enbMAR enbAC... Potential for error: may generate wrong control combinations (transfers that can never happen at the same time). Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultenously; => encode in single bit which is decoded rather than two separate bits NOTE: encoding should be such that parallel actions supported by datapath should be specifiable in a single microinstruction

19. ECE 232 L16.Microprog.19 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers More Vertical Format src dst DECDEC DECDEC other control fields next statesinputs MUX Some of these may have nothing to do with registers! Multiformat Microcode: 13 6 0condnext address 1333 1dstsrcalu DECDEC DECDEC Branch Jump Register Xfer Operation

20. ECE 232 L16.Microprog.20 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Hybrid Control Not all critical control information is derived from control logic E.g., Instruction Register (IR) contains useful control information, such as register sources (RS), destinations, opcodes, etc. Register File RS1DECRS1DEC RS2DECRS2DEC RDDECRDDEC op rs1 rs2rdIR to control enable signals from control

21. ECE 232 L16.Microprog.21 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal + more control over the potential parallelism of operations in the datapath - uses up lots of control store Vertical + easier to program, not very different from programming a RISC machine in assembly language - extra level of decoding may slow the machine down

22. ECE 232 L16.Microprog.22 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Designing a Microinstruction Set 1.Start with list of control signals 2.Group signals together that make sense: create “fields” 3.Places fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4.Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 5.To minimize the width, encode operations that will never be used at the same time

23. ECE 232 L16.Microprog.23 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers 1+2. Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC1st ALU operand = Reg[rs] RegWrite NoneReg. is written MemtoReg Reg. write data input = ALUReg. write data input = memory RegDst Reg. dest. no. = rtReg. dest. no. = rd TargetWrite NoneTarget reg. = ALU MemRead NoneMemory at address is read MemWrite NoneMemory at address is written IorD Memory address = PCMemory address = ALU IRWrite NoneIR = Memory PCWrite NonePC = PCSource PCWriteCond NoneIF ALUzero then PC = PCSource Single Bit Control ALUOp00ALU adds 01ALU subtracts 10ALU does function code 11ALU does logical OR ALUSelB0002nd ALU input = Reg[rt] 0012nd ALU input = 4 0102nd ALU input = sign extended IR[15-0] 0112nd ALU input = sign extended, shift left 2 IR[15-0] 1002nd ALU input = zero extended IR[15-0] PCSource00PC = ALU 01PC = Target 10PC = PC+4[29-26] : IR[25–0] << 2 Multiple Bit Control

24. ECE 232 L16.Microprog.24 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Start with list of control signals, cont’d ° For next state function (next microinstruction address), use sequencer-based control unit Called “microPC” or “µPC” vs. state register µaddress Select Logic Signal Effect 00 next µaddress = 0 01 next µaddress = dispatch ROM 10 next µaddress = µaddress + 1 Opcode microPC 1 Adder ROM Mux 0 012 Sequencing Datapath Microcode storage (ROM)

25. ECE 232 L16.Microprog.25 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers 3. Microinstruction Format: unencoded vs. encoded fields Field Name WidthControl Signals Set wide narrow ALU Control42ALUOp SRC121ALUSelA SRC253ALUSelB ALU Destination64RegWrite, MemtoReg, RegDst, TargetWr. Memory43MemRead, MemWrite, IorD Memory Register11IRWrite PCWrite Control54PCWrite, PCWriteCond, PCSource Sequencing32AddrCtl Total width3020bits

26. ECE 232 L16.Microprog.26 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers 4. Legend of Fields and Symbolic Names Field Name Field values Field function with specific value ALUAddALU adds Subt. ALU subtracts Func codeALU does function code OrALU does logical OR SRC1PC1st ALU input = PC rs1st ALU input = Reg[rs] SRC242nd ALU input = 4 Extend2nd ALU input = sign ext. IR[15-0] Extend02nd ALU input = zero ext. IR[15-0] Extshft2nd ALU input = sign ex., sl IR[15-0] rt2nd ALU input = Reg[rt] ALU destinationTargetTarget = ALUout rdReg[rd] = ALUout MemoryRead PCRead memory using PC Read ALURead memory using ALU output Write ALUWrite memory using ALU output Memory registerIRIR = Mem Write rtReg[rt] = Mem Read rtMem = Reg[rt] PC writeALUPC = ALU output Target-cond.IF ALU Zero then PC = Target jump addr.PC = PCSource SequencingSeqGo to sequential µinstruction FetchGo to the first microinstruction DispatchDispatch using ROM.

27. ECE 232 L16.Microprog.27 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Microprogram it yourself! LabelALU SRC1SRC2ALU Dest.MemoryMem. Reg. PC Write Sequencing FetchAddPC4Read PCIRALUSeq AddPCExtshftTargetDispatch LWAddrsExtend Seq Read ALUWrite rtFetch SWAddrsExtendSeq Write ALURead rtFetch RtypeFuncrsrtSeq rdFetch BEQ1Subt.rsrtTarget– cond.Fetch JUMP1jump addressFetch ORIOrrs Extend0 Seq rdFetch

28. ECE 232 L16.Microprog.28 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Overview of Control °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation PLAROM technique “hardwired control”“microprogrammed control”

29. ECE 232 L16.Microprog.29 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Microprogramming Pros and Cons °Ease of design °Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field °Can implement very powerful instruction sets (just more control memory) °Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. °Compatibility Many organizations, same instruction set °Costly to implement °Slow

30. ECE 232 L16.Microprog.30 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Summary °Specialize state-diagrams easily captured by microsequencer simple increment & “branch” fields datapath control fields °Control design reduces to Microprogramming °Exceptions are the hard part of control – to be discussed later °Need to find convenient place to detect exceptions and to branch to state or microinstruction that saves PC and invokes the operating system °As we get pipelined CPUs that support page faults on memory accesses which means that the instruction cannot complete AND you must be able to restart the program at exactly the instruction with the exception, it gets even harder