1. CS152 / Kubiatowicz Lec10.1 10/03/01©UCB Fall 2001 CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design (Continued) October 3, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

2. CS152 / Kubiatowicz Lec10.2 10/03/01©UCB Fall 2001 Partitioning the CPI=1 Datapath °Add registers between smallest steps °Place enables on all registers PC Next PC Operand Fetch Exec Reg. File Mem Access Data Mem Instruction Fetch Result Store ALUctr RegDst ALUSrc ExtOp MemWr nPC_sel RegWr MemWr MemRd Equal

3. CS152 / Kubiatowicz Lec10.3 10/03/01©UCB Fall 2001 Recap: Example Multicycle Datapath °Critical Path ? PC Next PC Operand Fetch Instruction Fetch nPC_sel IR Reg File Ext ALU Reg. File Mem Acces s Data Mem Result Store RegDst RegWr MemWr MemRd S M MemToReg Equal ALUctr ALUSrc ExtOp A B E

4. CS152 / Kubiatowicz Lec10.4 10/03/01©UCB Fall 2001 Recap: FSM specification IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ PC <= Next(PC) SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 00111011 1100 Execute Memory Write-back

5. CS152 / Kubiatowicz Lec10.5 10/03/01©UCB Fall 2001 Sequencer-based control unit: Statemachine ++ Opcode State Reg Inputs Outputs Control Logic Multicycle Datapath Types of “branching” Set state to 0 Dispatch (state 1) Use incremented state number 1 Adder Address Select Logic

6. CS152 / Kubiatowicz Lec10.6 10/03/01©UCB Fall 2001 Recap: Micro-controller Design °The state digrams that arise define the controller for an instruction set processor are highly structured °Use this structure to construct a simple “microsequencer” Each state in previous diagram becomes a “microinstruction” Microinstructions often taken sequentially °Control reduces to programming this device sequencer control datapath control micro-PC sequencer microinstruction (  )

7. CS152 / Kubiatowicz Lec10.7 10/03/01©UCB Fall 2001 Recap: Specific Sequencer from last lecture °Sequencer-based control unit from last lecture Called “microPC” or “µPC” vs. state register Control ValueEffect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 ROM: Opcode microPC 1 µAddress Select Logic Adder ROM Mux 0 012 R-type0000000100 BEQ0001000011 ori0011010110 LW1000111000 SW1010111011

8. CS152 / Kubiatowicz Lec10.8 10/03/01©UCB Fall 2001 Recap: Microprogram Control Specification 0000?inc1 00010load 00011inc 0010xzero1 1 0011xzero1 0 0100xinc0 1 fun 1 0101xzero1 00 1 1 0110xinc0 0 or 1 0111xzero1 00 1 0 1000xinc1 0 add 1 1001xinc1 0 1 1010 xzero1 01 1 0 1011xinc1 0 add 1 1100xzero 1 00 1 µPC TakenNext IRPCOpsExecMemWrite-Back en selA B Ex Sr ALU S R W MM-R Wr Dst R: ORi: LW: SW: BEQ

9. CS152 / Kubiatowicz Lec10.9 10/03/01©UCB Fall 2001 Recap: Overview of Control °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation PLAROM Technique “hardwired control”“microprogrammed control”

10. CS152 / Kubiatowicz Lec10.10 10/03/01©UCB Fall 2001 The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topics: Microprogramed control Administrivia Microprogram it yourself Exceptions Control Datapath Memory Processor Input Output

11. CS152 / Kubiatowicz Lec10.11 10/03/01©UCB Fall 2001 Microprogramming (Maurice Wilkes) °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

12. CS152 / Kubiatowicz Lec10.12 10/03/01©UCB Fall 2001 “Macroinstruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA...... User program plus Data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) one of these is mapped into one of these

13. CS152 / Kubiatowicz Lec10.13 10/03/01©UCB Fall 2001 Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points (remember ALU?) branch:µseq-opµadd execute:ALU-opA,B,R memory:mem-opS, D µseq µaddr A-mux B-mux bus enables register enables Horizontal Vertical

14. CS152 / Kubiatowicz Lec10.14 10/03/01©UCB Fall 2001 Extreme Horizontal input select N3N2 N1N0... 13 Incr PC ALU control 1 bit for each loadable register enbMAR enbAC... Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time. Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction

15. CS152 / Kubiatowicz Lec10.15 10/03/01©UCB Fall 2001 More Vertical Format src dst DECDEC DECDEC other control fields next statesinputs MUX Some of these may have nothing to do with registers! Multiformat Microcode: 13 6 1333 0condnext address 1dstsrcalu DECDEC DECDEC Branch Jump Register Xfer Operation

16. CS152 / Kubiatowicz Lec10.16 10/03/01©UCB Fall 2001 Hybrid Control Not all critical control information is derived from control logic E.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. Register File RS1DECRS1DEC RS2DECRS2DEC RDDECRDDEC op rs1 rs2rdIR to control enable signals from control

17. CS152 / Kubiatowicz Lec10.17 10/03/01©UCB Fall 2001 Vax Microinstructions VAX Microarchitecture: 96 bit control store, 30 fields, 4096 µinstructions for VAX ISA encodes concurrently executable "microoperations" USHFUALUUSUBUJMP 110636568958784 001 = left 010 = right. 101 = left3 010 = A-B-1 100 = A+B+1 00 = Nop 01 = CALL 10 = RTN Jump Address Subroutine Control ALU Control ALU Shifter Control Current intel architecture: 80-bit microcode, 8192  instructions

18. CS152 / Kubiatowicz Lec10.18 10/03/01©UCB Fall 2001 Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal + more control over the potential parallelism of operations in the datapath - uses up lots of control store Vertical + easier to program, not very different from programming a RISC machine in assembly language - extra level of decoding may slow the machine down

19. CS152 / Kubiatowicz Lec10.19 10/03/01©UCB Fall 2001 Administration °Midterm on Wednesday (10/10) from 5:30 - 8:30 in 277 Cory Hall No class on that day °Pizza and Refreshments afterwards at LaVal’s on Euclid I’ll Buy the pizza LaVal’s has an interesting history °Review Session: Sunday (10/7), 7:00 PM in 306 Soda???? Material through this Friday °Look over Lab 4 soon! Must email breakdown to your TA by Friday night at midnight

20. CS152 / Kubiatowicz Lec10.20 10/03/01©UCB Fall 2001 How Effectively are we utilizing our hardware? °Example: memory is used twice, at different times Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 °We could reduce HW without hurting performance extra control IR <- Mem[PC] A <- R[rs]; B<– R[rt] S <– A + B R[rd] <– S; PC <– PC+4; S <– A + SX M <– Mem[S] R[rd] <– M; PC <– PC+4; S <– A or ZX R[rt] <– S; PC <– PC+4; S <– A + SX Mem[S] <- B PC <– PC+4; PC < PC+4;PC < PC+SX;

21. CS152 / Kubiatowicz Lec10.21 10/03/01©UCB Fall 2001 “Princeton” Organization °Single memory for instruction and data access memory utilization -> 1.3/4.8 °Sometimes, muxes replaced with tri-state buses Difference often depends on whether buses are internal to chip (muxes) or external (tri-state) °In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle Reg File A B A- Bus B Bus IR S W-Bus PCPC next PC ZXSX Mem

22. CS152 / Kubiatowicz Lec10.22 10/03/01©UCB Fall 2001 Today: Alternative datapath (book) °Miminizes Hardware: 1 memory, 1 adder Ideal Memory WrAdr Din RAdr 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 01 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A

23. CS152 / Kubiatowicz Lec10.23 10/03/01©UCB Fall 2001 New Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 R-type ALUout <= A fun B R[rd] <= ALUout ALUout <= A or ZX R[rt] <= ALUout ORi ALUout <= A + SX R[rt] <= M M <= MEM[ALUout] LW ALUout <= A + SX MEM[ALUout] <= B SW “instruction fetch” “decode” Execute Memory Write-back 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 BEQ 0010 0011 If A = B then PC <= ALUout ALUout <= PC +SX Q: How improve to do something in state 0001?

24. CS152 / Kubiatowicz Lec10.24 10/03/01©UCB Fall 2001 Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 R-type ALUout <= A fun B R[rd] <= ALUout ALUout <= A or ZX R[rt] <= ALUout ORi ALUout <= A + SX R[rt] <= M M <= MEM[ALUout] LW ALUout <= A + SX MEM[ALUout] <= B SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 BEQ 0010 If A = B then PC <= ALUout ALUout <= PC +SX Execute Memory Write-back

25. CS152 / Kubiatowicz Lec10.25 10/03/01©UCB Fall 2001 Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals Use computers to design computers 5) To minimize the width, encode operations that will never be used at the same time

26. CS152 / Kubiatowicz Lec10.26 10/03/01©UCB Fall 2001 1&2) Start with list of control signals, grouped into fields Signal nameEffect when deassertedEffect when asserted ALUSelA1st ALU operand = PC1st ALU operand = Reg[rs] RegWriteNoneReg. is written MemtoRegReg. write data input = ALUReg. write data input = memory RegDstReg. dest. no. = rtReg. dest. no. = rd MemReadNoneMemory at address is read, MDR <= Mem[addr] MemWriteNoneMemory at address is written IorDMemory address = PCMemory address = S IRWriteNoneIR <= Memory PCWriteNonePC <= PCSource PCWriteCond NoneIF ALUzero then PC <= PCSource PCSource PCSource = ALU PCSource = ALUout ExtOpZero ExtendedSign Extended Single Bit Control Signal nameValueEffect ALUOp00ALU adds 01ALU subtracts 10ALU does function code 11ALU does logical OR ALUSelB002nd ALU input = 4 012nd ALU input = Reg[rt] 102nd ALU input = extended,shift left 2 112nd ALU input = extended Multiple Bit Control

27. CS152 / Kubiatowicz Lec10.27 10/03/01©UCB Fall 2001 Start with list of control signals, cont’d ° For next state function (next microinstruction address), use Sequencer-based control unit from last lecture Called “microPC” or “µPC” vs. state register Signal ValueEffect Sequen00Next µaddress = 0 -cing 01Next µaddress = dispatch ROM 10Next µaddress = µaddress + 1 ° Could even include “branch” option which changes microPC by adding offset when certain control signals are true. Opcode microPC 1 µAddress Select Logic Adder ROM Mux 0 012

28. CS152 / Kubiatowicz Lec10.28 10/03/01©UCB Fall 2001 3) Microinstruction Format: unencoded vs. encoded fields Field NameWidthControl Signals Set wide narrow ALU Control42ALUOp SRC121ALUSelA SRC253ALUSelB, ExtOp ALU Destination32RegWrite, MemtoReg, RegDst Memory32MemRead, MemWrite, IorD Memory Register11IRWrite PCWrite Control32PCWrite, PCWriteCond, PCSource Sequencing32AddrCtl Total width2415bits

29. CS152 / Kubiatowicz Lec10.29 10/03/01©UCB Fall 2001 4) Legend of Fields and Symbolic Names Field NameValues for FieldFunction of Field with Specific Value ALUAddALU adds Subt. ALU subtracts Func codeALU does function code OrALU does logical OR SRC1PC1st ALU input = PC rs1st ALU input = Reg[rs] SRC242nd ALU input = 4 Extend2nd ALU input = sign ext. IR[15-0] Extend02nd ALU input = zero ext. IR[15-0] Extshft2nd ALU input = sign ex., sl IR[15-0] rt2nd ALU input = Reg[rt] destinationrd ALUReg[rd] = ALUout rt ALUReg[rt] = ALUout rt Mem Reg[rt] = Mem MemoryRead PCRead memory using PC Read ALURead memory using ALUout for addr Write ALUWrite memory using ALUout for addr Memory registerIRIR = Mem PC writeALUPC = ALU ALUoutCondIF ALU Zero then PC = ALUout SequencingSeqGo to sequential µinstruction FetchGo to the first microinstruction DispatchDispatch using ROM.

30. CS152 / Kubiatowicz Lec10.30 10/03/01©UCB Fall 2001 Quick check: what do these fieldnames mean? CodeNameRegWriteMemToRegRegDest 00---0XX 01rd ALU101 10rt ALU100 11rt MEM110 CodeNameALUSelBExtOp 000---XX 001400X 010rt01X 011ExtShft101 100Extend111 111Extend0110 Destination: SRC2:

31. CS152 / Kubiatowicz Lec10.31 10/03/01©UCB Fall 2001 Alternative datapath (book): Multiple Cycle Datapath °Miminizes Hardware: 1 memory, 1 adder Ideal Memory WrAdr Din RAdr 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 01 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A

32. CS152 / Kubiatowicz Lec10.32 10/03/01©UCB Fall 2001 Microprogram it yourself! LabelALU SRC1SRC2ALU Dest.MemoryMem. Reg. PC Write Sequencing Fetch:AddPC4Read PCIRALUSeq

33. CS152 / Kubiatowicz Lec10.33 10/03/01©UCB Fall 2001 Microprogram it yourself! LabelALU SRC1SRC2Dest.MemoryMem. Reg. PC Write Sequencing Fetch:AddPC4Read PCIRALUSeq AddPCExtshftDispatch Rtype:FuncrsrtSeq rd ALUFetch Ori:Orrs Extend0 Seq rt ALUFetch Lw:AddrsExtend Seq Read ALU Seq rt MEM Fetch Sw:AddrsExtendSeq Write ALUFetch Beq:Subt.rsrt ALUoutCond.Fetch

34. CS152 / Kubiatowicz Lec10.34 10/03/01©UCB Fall 2001 Legacy Software and Microprogramming °IBM bet company on 360 Instruction Set Architecture (ISA): single instruction set for many classes of machines (8-bit to 64-bit) °Stewart Tucker stuck with job of what to do about software compatibility °If microprogramming could easily do same instruction set on many different microarchitectures, then why couldn’t multiple microprograms do multiple instruction sets on the same microarchitecture? °Coined term “emulation”: instruction set interpreter in microcode for non-native instruction set °Very successful: in early years of IBM 360 it was hard to know whether old instruction set or new instruction set was more frequently used

35. CS152 / Kubiatowicz Lec10.35 10/03/01©UCB Fall 2001 Microprogramming Pros and Cons °Ease of design °Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field °Can implement very powerful instruction sets (just more control memory) °Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. °Compatibility Many organizations, same instruction set °Costly to implement °Slow

36. CS152 / Kubiatowicz Lec10.36 10/03/01©UCB Fall 2001 An Alternative MultiCycle DataPath °In each clock cycle, each Bus can be used to transfer from one source °µ-instruction can simply contain B-Bus and W-Dst fields Reg File A B A-Bus B Bus IR S mem W-Bus PCPC inst mem next PC ZXSX

37. CS152 / Kubiatowicz Lec10.37 10/03/01©UCB Fall 2001 What about a 2-Bus Microarchitecture (datapath)? Reg File A B A- Bus B Bus IR S PCPC next PC ZXSX Mem Reg File A B IR S PCPC next PC ZXSX Mem Instruction Fetch Decode / Operand Fetch M M

38. CS152 / Kubiatowicz Lec10.38 10/03/01©UCB Fall 2001 Load °What about 1 bus ? 1 adder? 1 Register port? Reg File A B IR S PCPC next PC ZXSX Mem Reg File A B IR S PCPC next PC ZXSX Mem Reg File A B IR S PCPC next PC ZXSX Mem Execute addr M M M Mem Write-back

39. CS152 / Kubiatowicz Lec10.39 10/03/01©UCB Fall 2001 Summary °Specialize state-diagrams easily captured by microsequencer simple increment & “branch” fields datapath control fields °Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) °Steps: identify control signals, group them, develop “mini language”, then microprogram °Control design reduces to Microprogramming Arbitrarily complicated instructions possible

40. CS152 / Kubiatowicz Lec10.40 10/03/01©UCB Fall 2001 Summary: Microprogramming one inspiration for RISC °If simple instruction could execute at very high clock rate… °If you could even write compilers to produce microinstructions… °If most programs use simple instructions and addressing modes… °If microcode is kept in RAM instead of ROM so as to fix bugs … °If same memory used for control memory could be used instead as cache for “macroinstructions”… °Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine?