1. Technology Mapping 1 Outline –What is Technology Mapping? –Rule-Based Mapping –Tree Pattern Matching Goal –Understand technology mapping –Understand mapping algorithms –Understand mapping issues Reading –CPSC 464 Lecture Notes

2. What is Technology Mapping? Map optimized logic to primitive cell library Library capabilities –function –cell size –cell performance Library restrictions –fan-in –fan-out Goal –delay –area –power –etc. Cell AOI33 - area 3248 - delay 0.8 - power 0.08

3. Cell Libraries Custom cells –synthesize functions as needed –e.g. complementary, domino, or CVSL CMOS Standard cells –library of fixed functions –use as needed –e.g. 3-input AND-OR Gate arrays –fixed population of gates and gate types –must fit design into available gates FPGAs –programmable function blocks –e.g. all functions of 4 inputs ab a b ab

4. Custom Cell Synthesis Mechanically transform function to custom cell –complementary CMOS - cell is guaranteed to work »but it might be slow - e.g. 20-input NAND gate –avoid problems by limiting functions in synthesis process »limit fan-in, fan-out of functions »chop up large functions Apply electrical rules –size transistors to meet timing goals –speed up longest paths in circuit –rules are specific to cell technology ABCDEF => (ABC)(DEF) A+B+C+D => (A+B)+(C+D) ab a b ab in series, so make fatter speeds up 1->0 transition

5. Rule-Based Cell Matching Library-based transformations –rules encode library capabilities and restrictions –transformations improve area, delay, power, etc. –similar to synthesis via local optimization SOCRATES circuit optimizer –lookahead several rules –test all applicable rules »avoid local minima Problems –rules are not guaranteed to find optimum –rules may not be complete XX

6. Rule-Based Matching Algorithm TryRule3(circuit, rule) { scan circuit for rule match if match, compute cost recurse twice more on all rules return minimum cost } do { mincost = cost; for (i = 0; i < MAXRULES; i++) { cost = TryRule3(circuit, rule[i]); if (cost < mincost) { mincost = cost; minrule = rule[i]; } if (minrule != NULL) cost = ApplyRule(circuit, minrule); } until no rules apply Complexity (CN) 3 for C circuit elements and N rules

7. Graph Covering Logic Equation Representation –directed acyclic graphs (DAGs) »2-input NANDs and inverters in MIS »representation is not unique Library Cell Representation –represent cells as DAGs »2-input NANDs and inverters in MIS »all decompositions of a cell function »~N! possibilities for N inputs –cell cost (area, delay, power) abdc F F = abcd a b dc F NAND NOT d c ba F b d ca F

8. Graph Covering abdc F F = abcd a b dc F Algorithm –minimum-cost cover of equation DAGs with library DAGs –NP-complete (Bruno and Sethi 1975) –same problem as compiler code generation Approaches –search from primary inputs –search from primary outputs –try largest cell DAGs first »usually smallest area »not always fastest »similar to “maximal munching” in code generation –avoid local minima »lookahead »several random starting points