1. Spring 07, Mar 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 A Linear Programming Solution to Clock Constraint Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

2. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)2 A General Sequential Circuit Combinational Logic Registers Clock InputsOutputs

3. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)3 A Level-Sensitive Latch D CK Q QN Clock period, Tck CK time Latch openLatch closedLatch open

4. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)4 Alternative Implementation D CK Q J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Wiley Interscience, 2004, p.137.

5. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)5 Data Must be Stable Before Latch Closes 1 1 0 0 1 D = 0 → 1 CK = 1 → 0 Q QN Clock period, Tck CK time Latch openLatch closed 0→1→0→0→ 1→1→0→0→ 0→0→1→0→1→ 1→0→1→0→1→ Unstable state Stable data delays

6. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)6 Data and Clock Parameters Clock period, Tck CK time Latch openLatch closed D time Stable data Stable Q Q time Setup time Hold time CK-to-Q delay

7. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)7 Design With Level-Sensitive Latches Comb. Logic Level-sens. Latches PI PO Comb. Logic Level-sens. Latches PI PO CK

8. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)8 Edge-Triggered Flip-flop D CK Q QN Clock period, Tck CK time Master openSlave open Master latchSlave latch Trigger edges Setup time Hold time CK-to-Q

9. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)9 A Dynamic Implementation D Q CK VDD GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 229.

10. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)10 A Static Implementation D Q CK VDD GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 230.

11. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)11 Design With Edge-Triggered Flip-Flops Combinational Logic Flip-flops Clock InputsOutputs

12. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)12 Setup Time Constraint FF iFF j Combinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j) TsiThi Tqi Clock edge time Tck Tsj Constraint:Tqi + Δ(i,j)≤Tck – Tsj i.e., Δ(i,j)≤Tck – Tsj – Tqi This is known as long path constraint. Note: All times for a FF should be adjusted by its clock skew.

13. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)13 Hold Time Constraint FF iFF j Combinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j) TsiThi Tqi Clock edge time Tck Tsj Constraint:Tqi + δ(i,j)≥Thj i.e., δ(i,j)≥Thj – Tqi Thj This is known as short path constraint. Note: All times for a FF should be adjusted by its clock skew.

14. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)14 Solving Hold Time Problem (1) PO (FFi) PO (FFj) PI (FFi) PI (FFj) PO PI Fanout node Internal edges (fixed delays) External edges (variable delays)

15. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)15 Solving Hold Time Problem (2)  Variables:  Earliest arrival time at node i = ai  Longest arrival time at node i = Ai  Buffer delays on external edge (i,j) = wij  Constants:  At PI i: Ai = Λi and ai = λi, user specified.  At PI (FF) i: Ai = ai = Tqi

16. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)16 Solving Hold Time Problem (3)  Constraints:  At PO i: Ai ≤ Ri and ai ≥ ri, user defined.  At PO (FF) i:  ai ≥ Thi, short path constraint.  Ai ≤ Tck – Tsi, long path constraint.  Optimization function (a linear approximation to minimum number of delay buffers): minimize ∑ wij all external edges (i,j)

17. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)17 Linear Programming Solution (1) minimize ∑ wij all external edges (i,j) Subject to:Aj ≥ Ai + wijfor all i ε Fanin(j) aj ≤ ai + wijfor all i ε Fanin(j) Ai ≤ Rifor all i ε PO ai ≥ rifor all i ε PO Ai ≤ Tck – Tsi for all i ε PO(FF i) ai ≥ Thi for all i ε PO(FF i) Ai = Λifor all i ε PI ai = λifor all i ε PI Ai = Tqifor all i ε PI(FF i) ai = Tqi for all i ε PI(FF i)

18. Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)18 Linear Programming Solution (2)  Solution inserts smallest delays in interconnects to satisfy short path constraints.  Maintains the specified clock period and satisfies setup time constraints. Reference:N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.