1. Chapter 5 Internal Memory

2. Semiconductor Memory Types

3. Static RAM (SRAM)
Desired for main memory
Used in cache
Basically an array of flip-flops
Simple to interface and control
Fast
Relatively low density - complex
Relatively expensive

4. Static RAM model

5. Semiconductor Memory
What is it ?

6. 2 BIT Decoder (2 to 4)

7. 3 Bit Decoder (3 to 8) ?
4 Bit Decoder (4 to 16) ?

8. 2 to 4 Bit Decoder

9. 3 to 8 Bit Decoder

10. 2 to 1 MUX

11. 4 to 1 MUX

12. 8 to 1 MUX

13. 16 to 1 MUX ?

14. Register

15. 22 x 3 Memory word select word WE input bits address write enable
Decoder asserts one of the word select lines, based on address.
Word select activates one of the output AND gates, which drives the selected data to the output OR gate. (For a read, this is basically a MUX -- decoder ANDed with signals, results ORed together.)
When writing, the only WE bits for the proper word are asserted (based on decoder again).
address
decoder
output bits

16. 24 x 8 Memory ?

17. Dynamic RAM (DRAM) Used in main memory
Bits stored as charge in capacitors
Essentially analog device
Charges leak
Need refreshing even when powered
Need refresh circuits
Higher density (more bits per chip)
Slower than Static RAM
Less expensive

18. Dynamic RAM model

19. Microprogramming (see later) Library subroutines
Read Only Memory (ROM)
Permanent storage
Nonvolatile
Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables

20. ROM: Written during manufacture
Types of ROM
ROM: Written during manufacture
Very expensive for small runs
PROM: Programmable (once)
Needs special equipment to program
Read “mostly”
EPROM: Erasable Programmable
Erased by UV
EEPROM: Electrically Erasable
Takes much longer to write than read
Flash memory
Erase whole memory (block) electrically

21. EPROM

22. A 16Mbit chip can be organised as 1M of 16 bit words
Memory Organization
A 16Mbit chip can be organised as 1M of 16 bit words
A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on
A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4 capacity

23. Typical 16 Mb DRAM (4M x 4)

24. Semiconductor Memory
16Mbit DRAM

25. Refreshing
Refresh circuit is included on the chip
Count through rows
Read & Write back
Chip must be disabled during refresh
Takes time
Slows down apparent performance

26. 256kByte Module Organisation (256K x 1)

27. 1MByte Module Organization (1Meg x 8 bits)