1. CMOS Technology: How are chips fabricated?
EE116B (Winter 2004): Lecture #2

2. References for this Lecture
“How chips are made” – Intel
“Microelectronics 101” – IBM
[Adapted from Copyright 1996 UCB]

3. Ingredients of Chip Making
Silicon Wafers cut from an ingot of pure silicon, are used by Intel to make microprocessors. Silicon, the primary ingredient of beach sand, is a semiconductor of electricity. Semiconductors are materials that can be altered to be either a conductor or an insulator.
Chemicals and gases are used throughout the chip-making process. Some, like hexamethyldisilazane, are complex and difficult to pronounce. Others, such as boron, are simple elements found in the Periodic Table of the Elements.
Metals, such as aluminum and copper, are used to conduct the electricity throughout the microprocessor. Gold is also used to connect the actual chip to its package.
Ultraviolet (UV) Light has very short wavelengths and is just beyond the violet end of the visible spectrum. UV light is used to expose patterns on the layers of the microprocessor in a process much like photography.
Masks used in the chip-making process are like stencils. When used with UV light, masks create the various circuit patterns on each layer of the microprocessor.
[Courtesy Intel. Adapted from

4. How is CMOS built? Start with a disk of silicon called wafer
75 mm to 230 mm in diameter, < 1 mm thick
cut from ingots of single-crystal silicon
pulled from a crucible of pure molten polycrystalline silicon using a seed crystal
Different processing steps and techniques
Introduce dopants
Oxidation
Masking
Polysilicon

5. Introduce Dopants Pure silicon is a semiconductor
bulk electrical resistance in between that of a conductor and insulator
Conductivity of silicon can be varied several orders of magnitude by introducing impurity atoms
called dopants
acceptors: accept electrons to leave holes in silicon
lead to p-type silicon (e.g. Boron)
donors: provide electrons to silicon
lead to n-type silicon (e.g. Arsenic, Phosphorous)

6. Introduce Dopants (2) Deposition through diffusion Ion Implantation
evaporating dopant material into the silicon surface
thermal cycle: impurities diffuse deeper into material
Ion Implantation
silicon surface subjected to highly energized donor or acceptor atoms
atoms impinge silicon surface, and drive below it to form regions of varying concentrations
Epitaxy
growing a single-crystal film on the silicon surface
silicon wafer subjected to elevated temperatures and a source of dopant material
Ion Implantation

7. Oxidation
Method 1: Heating silicon wafers in an oxidizing atmosphere (O2 or H2O)
Consumes Si
Grows equally in both vertical directions
Method 2: Deposition
Deposited on top of existing layers

8. Masking Masks act as barrier against e.g. Commonly used mask materials
ion implantation
dopant deposition before diffusion (dopants do not reach surface)
oxidation (O2 or H2O does not reach surface)
Commonly used mask materials
photoresist
polysilicon
silicon dioxide (SiO2)
silicon nitride (SiN)

9. Example: oxide mask bare silicon wafer oxidize wafer
deposit layer of photoresist
expose the photoresist selectively to UV light
The drawn mask pattern determines which part is exposed
Resist polymerizes where exposed

10. unexposed resist is removed with solvent: negative resist
(positive resist: exposed resist is removed)
exposed oxide is etched
photoresist is washed off
the oxide can now be used as a masking layer for ion implantation
UV lithography: line width limited by diffraction and alignment tolerances, but tricks are used
Electron beam lithography has emerged: directly from digital data, but more costly and slow

11. Polysilicon Silicon also comes in a polycrystalline form Used as
called polysilicon, or just poly
high resistance
normally doped at the same time as source/drain regions
Used as
an interconnect in silicon ICs
gate electrode in MOS transistors
most important: acts as a mask to allow precise definition of source and drain extension under gate
minimum gate to source/drain overlap improves circuit performance (why?)
called self-aligned process

12. Construction of Transistors
Depends on ability to control
what type  dopant source
how many  energy, time, temperature etc.
where  using special material as “masks”
of impurities are introduced into silicon wafer

13. Simplified View of CMOS Fabrication Process

14. A Basic N-well CMOS Process
Create oxide mask (see slide 8) using the well-mask
Implant the N-well
Etch away the oxide mask
Grow the thin oxide (gate oxide) over the entire wafer
Deposit a SiN (nitride layer) and pattern it with the mask for the active areas (n and p diffusion): defines where the transistors will be

15. Etch away the oxide where it is exposed
Deposit resist patterned by the well-mask
Channel stop implants: make substrate more p+ (why?)
(active areas are protected by the nitride-oxide layer)

16. Remove resist and grow field oxide (nitride protects the thin oxide)
Etch nitride
Deposit polysilicon
Apply photoresist with poly-mask and etch poly

17. Use n+ mask to leave only the regions where nmos tors are wanted free (also called the select mask)
Implant the n dopants: self-aligned process
Channel is masked from S and D by the gate
Poly is also implanted (needed to improve conductivity)
Remove masking material

18. Remark: sometimes more complex S/D structures are used
(LDD: lightly doped drain)
Complementary of n+ mask is used to define p+ areas

19. Oxide deposition
Apply resist using contact-mask and etch contact holed
Deposit metal
Apply resist using metal-mask and etch metal interconnects

20. Repeat steps q-t for multiple metal layers
Passivate wafer (protect again environment, contaminants)
Etch openings for bonding pads to allow for connection to the package

21. CMOS Inverter in N-well Process

22. Substrate & Well Contacts
In N-well process
p-type substrate is connected to VSS
p+ regions
well is connected to VDD
n+ regions
Called:
well contacts
substrate contacts

23. Latch-up

24. Latch-up (contd.)

25. Guard Rings

26. P-well Process P-well processes were common in early days
N-well is more popular now
P-well preferred where NMOS and PMOS characteristics need to be more balanced
transistor that resides in well tends to have inferior characteristics as compared to transistor in native substrate
P-well has better PMOS than a N-well process

27. Twin-Well Processes Allow separate optimization of NMOS and PMOS
independent optimization of threshold voltage, body effect, gain, etc.

28. Silicon on Insulator Insulating substrate (e.g. sapphire) Advantages
no latch-up problems
speed due to lower parasitic substrate capacitance
closer packing of NMOS and PMOS transistors
power advantage: no leakage current

29. CMOS Process Enhancements for Better Interconnect
Process enhancements to
ease routing, especially automated routing
improve power and clock distribution
Enhancements include:
additional layers of metal (2,3, or more)
additional layers of poly (2, 3, or more)
improving existing layer of poly
reduce sheet resistance of poly (20-40 ) by combining it with a refractory metal (e.g. silicon & tantalum)
improving existing layer of metal
copper instead of aluminum

30. Two-level Metal Process
Normally Aluminum is used for metal layers
As vertical topology becomes more varied, the width and spacing of conductors has to increase
to avoid conductors becoming too thin, and hence break, at vertical topology jumps

31. Two-level metal Via/Contact Geometries
Via to connect M1 & M2
Separation between via & contact to diff or poly
M1 must be involved in contact to diff or poly
M1 & M2 borders required around via
Restrictions on placement of via

32. Polysilicon/Refractory Metal Interconnect
Goal is to allow the gate material to be used as a moderate long-distance interconnect

33. Advanced Metallization
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

34. CMOS Layout Rules scalable design rules: lambda parameter
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

35. Example CMOS Layout Rules

36. Example CMOS Layout Rules (contd.)

37. Example CMOS Layout Rules (contd.)

38. CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color
Representation
Yellow
Green
Red
Blue
Magenta
Black
Select (p+,n+)
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

39. Layers in 0.25 mm CMOS process
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

40. Intra-Layer Design Rules4
Metal2 3
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

41. Transistor Layout
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

42. Vias and Contacts
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

43. Select Layer
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

44. CMOS Inverter Layout
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

45. Layout Editor
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

46. Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

47. Sticks Diagram 1 V 3 In Out GND Dimensionless layout entities
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

48. Future of IC Technology?
L. Geppert. The amazing vanishing transistor act. IEEE Spectrum, October pp
R.D. Isaac. The future of CMOS technology. IBM Journal of Research & Development, May pp
T.H. Lee.A vertical leap for microchips. Scientific American, January
Beyond transistors: organic, molecular, quantum …

49. N-well CMOS Design Rules

50. N-well CMOS Design Rules (contd.)

51. N-well CMOS Design Rules (contd.)

52. N-well CMOS Design Rules (contd.)

53. N-well CMOS Design Rules (contd.)

54. N-well CMOS Design Rules (contd.)

55. N-well CMOS Design Rules (contd.)

56. CMOS Inverter in N-Well

57. CMOS Inverter in N-Well

58. CMOS Inverter in N-Well

59. Merged or Abutting Substrate Contact