1. Microprocessors Introduction to ia32 Architecture Jan 31st, 2002

2. Memory Structure Addressable units Addressable units Ia32 is byte addressed, with 8-bit Ia32 is byte addressed, with 8-bit Memory size Memory size 4 gigabytes (2**32 bytes) 4 gigabytes (2**32 bytes) Form of Addresses Form of Addresses Segmented, segment address can be implicit Segmented, segment address can be implicit Offset up to 2**32 Offset up to 2**32

3. More on Memory Size But chip also operates in 8086 mode But chip also operates in 8086 mode Memory size limited to 1 gigabyte, segmented with an offset into the segment of only 64K bytes. Memory size limited to 1 gigabyte, segmented with an offset into the segment of only 64K bytes. Chip Also operates in 80286 mode Chip Also operates in 80286 mode Memory size limited to 16 gigabytes, segmented with offsets into segment of 64K bytes (but more segments allowed than in 8086 mode). Memory size limited to 16 gigabytes, segmented with offsets into segment of 64K bytes (but more segments allowed than in 8086 mode).

4. Data Formats Hardware support on ia32 Hardware support on ia32 Integer formats Integer formats Floating formats Floating formats Character Formats Character Formats Pointer/Address formats Pointer/Address formats Other types Other types

5. Integer Formats Sizes supported (1,2,4byte) Sizes supported (1,2,4byte) Unsigned and Signed Unsigned and Signed Signed format is 2’s complement Signed format is 2’s complement Little-endian Little-endian Little-endian has least significant byte at lowest address Little-endian has least significant byte at lowest address No big-endian operation possible, but there is a byte swap instruction. No big-endian operation possible, but there is a byte swap instruction.

6. Floating Formats Uses “IEEE” formats Uses “IEEE” formats IEEE = IEEE standard 754/854 IEEE = IEEE standard 754/854 Provides 32- and 64-bit standard formats Provides 32- and 64-bit standard formats Two quite different instruction sets Two quite different instruction sets Old style (“8087”) also has 80-bit format Old style (“8087”) also has 80-bit format New style is only 32 and 64 bit New style is only 32 and 64 bit

7. Character Formats No specific instructions that know anything about character formats No specific instructions that know anything about character formats But instructions are provided for conveniently working with strings of 8-bit and 16-bit “characters” But instructions are provided for conveniently working with strings of 8-bit and 16-bit “characters” String move String move String scan and compare String scan and compare String store String store

8. Pointer/Address Formats Used to hold address of memory location Used to hold address of memory location Usually we work entirely within a single segment on the ia32 Usually we work entirely within a single segment on the ia32 So pointers are just an offset in the segment which is a 32-bit unsigned word So pointers are just an offset in the segment which is a 32-bit unsigned word But a full pointer format is a segment number (16 bits) + a 32 bit offset But a full pointer format is a segment number (16 bits) + a 32 bit offset No one uses this format in practice No one uses this format in practice

9. Other Formats Remember we are talking hardware here Remember we are talking hardware here Packed decimal Packed decimal Two decimal digits stored in one byte Two decimal digits stored in one byte For example 93 stored as hexadecimal 93 For example 93 stored as hexadecimal 93 Used by COBOL programs Used by COBOL programs Provided by the “8087” mode floating-point unit Provided by the “8087” mode floating-point unit Fractional binary (not supported) Fractional binary (not supported) Special graphics/multimedia formats Special graphics/multimedia formats Interesting capabilities, to look at later Interesting capabilities, to look at later Vector/array processing (limited capabilities) Vector/array processing (limited capabilities)

10. Data Alignment Data alignment is not required, except for the new style of floating-point. What happens if data is misaligned Data alignment is not required, except for the new style of floating-point. What happens if data is misaligned Works, but slower. How much slower? Works, but slower. How much slower? Depends, not too bad for integer, but can be very significant for floating-point Depends, not too bad for integer, but can be very significant for floating-point Keep stuff aligned if at all possible, this is more and more important as time goes on Keep stuff aligned if at all possible, this is more and more important as time goes on

11. General Register Structure Eight 32-bit Integer registers Eight 32-bit Integer registers eax, ebx, ecx, edx, esi, edi, ebp, esp eax, ebx, ecx, edx, esi, edi, ebp, esp Can also use low order 16 bits of register Can also use low order 16 bits of register ax, bx, cx,dx, dx, si, di, bp, sp ax, bx, cx,dx, dx, si, di, bp, sp Can also use low order 8 bits of some registers Can also use low order 8 bits of some registers al, bl, cl, dl al, bl, cl, dl Used for characters, integers, pointers, basically everything except floating-point values. Used for characters, integers, pointers, basically everything except floating-point values. Every register has special purpose Every register has special purpose For example, ECX used by LOOP instruction For example, ECX used by LOOP instruction ESP is stack pointer ESP is stack pointer ESI is source pointer for string move instruction ESI is source pointer for string move instruction

12. Segment Registers Six segment registers Six segment registers ES, DS, CS, SS, FS, GS ES, DS, CS, SS, FS, GS From user point of view hold a 16-bit segment number, but in fact are large registers holding a complete segment description From user point of view hold a 16-bit segment number, but in fact are large registers holding a complete segment description Usually used implicitly Usually used implicitly CS used for all code CS used for all code SS used for all stack references SS used for all stack references DS used for all data references DS used for all data references But can be used explicitly in instructions But can be used explicitly in instructions Almost never used in ia32 mode Almost never used in ia32 mode

13. Flag Registers A series of one-bit registers A series of one-bit registers CF – carry flag CF – carry flag SF – sign flag SF – sign flag OF – overflow flag OF – overflow flag ZF – zero flag ZF – zero flag Etc. Etc. Set by instructions, e.g. add instruction sets flags implicitly: Set by instructions, e.g. add instruction sets flags implicitly: CF if carry CF if carry ZF if result is zero ZF if result is zero OF if result is 2’s complement signed overflow OF if result is 2’s complement signed overflow

14. Specialized Registers System registers System registers State of floating-point unit State of floating-point unit Rounding mode Rounding mode Precision mode, etc. Precision mode, etc. Debug registers Debug registers Data and instruction debug registers Data and instruction debug registers Other Special registers Other Special registers Interrupt handling Interrupt handling Segment table and task handling Segment table and task handling

15. Instruction Set What set of operations are available What set of operations are available Gigantic set of all kinds of specialized stuff Gigantic set of all kinds of specialized stuff E.g. instruction for handling addressing in nested subprograms. E.g. instruction for handling addressing in nested subprograms. Instructions for handling task switching Instructions for handling task switching String move/compare String move/compare Decimal addition adjustment Decimal addition adjustment What memory reference instructions What memory reference instructions Many instructions can reference memory, e.g. increment, add to/from memory etc. Many instructions can reference memory, e.g. increment, add to/from memory etc.

16. Addressing Modes Direct addressing (address in instruction) Direct addressing (address in instruction) Full direct addressing (long instructions. Full direct addressing (long instructions. Indirect through register (simple indexing) Indirect through register (simple indexing) Many other addressing modes Many other addressing modes

17. Other Addressing Modes Index + Offset (offset in the instruction) Index + Offset (offset in the instruction) Offset is 8, 16, or 32 bits (long instructions) Offset is 8, 16, or 32 bits (long instructions) Double indexing (two regs added) Double indexing (two regs added) Double indexing + offset Double indexing + offset Offset is 8, 16, or 32 bits Offset is 8, 16, or 32 bits Scaling (register multipled by 2,4,8 …) Scaling (register multipled by 2,4,8 …) One of the two registers in double indexing can be scaled by 2, 4, or 8. One of the two registers in double indexing can be scaled by 2, 4, or 8.

18. Instruction Formats How many different instruction formats How many different instruction formats Dozens of different instruction formats Dozens of different instruction formats No systematic organization at all No systematic organization at all Fixed vs Variable size instructions Fixed vs Variable size instructions Variable length Variable length Uniform vs non-uniform formats Uniform vs non-uniform formats Highly non-uniform Highly non-uniform Size of instructions Size of instructions 1-12 byte instructions 1-12 byte instructions

19. Instruction Level Parallelism Can instructions execute in parallel? Can instructions execute in parallel? Yes, but this is completely invisible to the programmer Yes, but this is completely invisible to the programmer Program executes as though instructions were executed in sequence one by one Program executes as though instructions were executed in sequence one by one No branch delay slots or any other visible parallelism No branch delay slots or any other visible parallelism This is because of compatibility This is because of compatibility Original machines, e.g. 8086, 80286, and 80386, worked this way Original machines, e.g. 8086, 80286, and 80386, worked this way

20. Traps What instructions cause traps What instructions cause traps Addressing traps Addressing traps Overflow traps Overflow traps Divide by zero Divide by zero Are traps strictly synchronous? Are traps strictly synchronous? Yes, they appear to be Yes, they appear to be How does machine handle trap? How does machine handle trap? Later … Later …

21. Interrupts How are external interrupts handled How are external interrupts handled Later … Later … Multiple levels of interrupts Multiple levels of interrupts Yes Yes Interrupt priorities Interrupt priorities Yes Yes Mechanisms for handling interrupts Mechanisms for handling interrupts Later … Later …

22. Modes of Operation Kernel/supervisor/system mode vs application/program mode Kernel/supervisor/system mode vs application/program mode Four different levels Four different levels Rings of protection Rings of protection Inner ring 0 no restrictions Inner ring 0 no restrictions Outer ring 3 full restrictions Outer ring 3 full restrictions For Example, no I/O For Example, no I/O No messing with segment tables No messing with segment tables No messing with virtual memory tables No messing with virtual memory tables How does operation switch from one mode to another? How does operation switch from one mode to another? Later.. Later..

23. Handling of I/O Input/Output Instructions Input/Output Instructions Later … Later … Input/Output Channels Input/Output Channels Interaction with processing modes Interaction with processing modes Interrupt handling Interrupt handling

24. Memory Handling Virtual memory handling Virtual memory handling Virtual address = 32 bits Virtual address = 32 bits Physical address = 32 bits Physical address = 32 bits Mapping uses multi-level tables Mapping uses multi-level tables Handled entirely by hardware Handled entirely by hardware

25. Caching Issues Mostly a matter of implementation rather than architecture. Mostly a matter of implementation rather than architecture. Caching not visible to ordinary programs Caching not visible to ordinary programs

26. Parallel Processing Issues Consider building machine with more than one processor Consider building machine with more than one processor Later … Later …

27. Implementation Issues Does architecture assume specific implementation details Does architecture assume specific implementation details Scheduling Scheduling Caching Caching Pipelining Pipelining Answer is no to all of the above, since high level of compatibility maintained between many different implementations Answer is no to all of the above, since high level of compatibility maintained between many different implementations

28. Compiler Issues How is code generated for this machine? How is code generated for this machine? Hard work, because so non-uniform Hard work, because so non-uniform Any special problems? Any special problems? Highly non-uniform registers Highly non-uniform registers Too few registers Too few registers Any special features designed to make translation of specific features easier? Any special features designed to make translation of specific features easier? Yes, but they don’t help much Yes, but they don’t help much

29. Operating Systems Issues How is an Operating System for this machine constructed? How is an Operating System for this machine constructed? Later … Later … Any special features designed to make the life of an OS easier? Any special features designed to make the life of an OS easier? Yes, special instructions for task swiching, state saving, multiple processes accessing virtual memory etc. Yes, special instructions for task swiching, state saving, multiple processes accessing virtual memory etc. But they don’t help much! But they don’t help much!

30. End of Lecture See you next Tuesday See you next Tuesday Send any problems to class list Send any problems to class list (see class page for how to sign up) (see class page for how to sign up) Assignment: send one message to class list Assignment: send one message to class list Either an interesting question, or just hello! Either an interesting question, or just hello! These slides will be up on the Web in HTML and Power point formats These slides will be up on the Web in HTML and Power point formats