1. 7 January 2005MDI Workshop M. Breidenbach1 SLD VXD3 Pickup Experience

2. 7 January 2005MDI Workshop M. Breidenbach2 VXD3 Overall Layout

3. 7 January 2005MDI Workshop M. Breidenbach3 CCD ladder details

4. 7 January 2005MDI Workshop M. Breidenbach4 VXD3 Layout

5. 7 January 2005MDI Workshop M. Breidenbach5 VXD3 half

6. 7 January 2005MDI Workshop M. Breidenbach6 On CCD Preamp

7. 7 January 2005MDI Workshop M. Breidenbach7 Overall Electronics Layout

8. 7 January 2005MDI Workshop M. Breidenbach8 Basic Signal Processing

9. 7 January 2005MDI Workshop M. Breidenbach9 Beam Pickup Beam synchronous interference (data and control) between the GLinks on the FE boards and the Data Acq boards. –Extensive struggles with grounding did not affect the problem. –The FE boards use a PLL to recover the 60 MHz clock. Loss of lock generated a board reset – so the PLL “not-locked” signal was disconnected. This is evidence for a long, local disruption of the clock system. –Another problem was interference with the decoded clock modulation generating spurious control commands. “Fixed” problem by implementing a 10 μsec blanking signal during which the FE boards ignored any commands around beam crossing time. We do not understand the origin of this interference, and it might be far upstream. Since the rest of SLD already had beam synchronous readout, we might not have been sensitive to pickup. (VXD2 had preamps driving cables to an accessible area. Beam pickup was observed, but it was not a problem for data)