Presentation is loading. Please wait.

Presentation is loading. Please wait.

Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:March 4, 2004.

Similar presentations


Presentation on theme: "Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:March 4, 2004."— Presentation transcript:

1 Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:March 4, 2004

2 Presentation Outline Project Summary Functional Description Detailed Description Review of Previous Work Laboratory Results Semester Schedule

3 Project Summary Creation of a frequency synthesizer –Use of direct synthesis approach

4 Project Summary System Characteristics –Output Frequencies of 3650, 3700, 3850, 3900, 4450, 4500, 4650, and 4700 MHz –Output Power of 0 dBm, ± 3 dB –Output Spurs < -45 dBc –Tuning Time < 500 ns, 200 ns if possible –Use of an External 100 MHz Reference Signal

5 Functional Description Fast Tuning Frequency Synthesizer 3.6 – 4.6 GHz 100 MHz Reference D2 D1 D0 Digital Input Command Desired Output Frequency

6 Detailed Description

7 Input Module

8

9 Resolution Modules

10

11 Basis Frequency Modules

12

13 Switch Selection Module

14

15 Output Module

16

17 Laboratory Work - Review Designed and Simulated Ideal Chebyshev Filters –Used Insertion Loss Method –Developed Low-Pass Filter Prototype –Transformed to Band-Pass Filter Added Parasitic Effects –Real Component Values –Real Inductor Responses –Microstrip Transmission Effects –Via Connections

18 Laboratory Work - Review

19

20

21

22

23

24 Determined and Ordered Necessary Parts

25 Laboratory Work Created PCB Layouts for Filter Boards Fabricated, Populated, and Tested Filter Boards Developed Modular Layout Plan Currently Creating PCB Layouts for Components

26 Laboratory Work

27

28 Dark Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Aqua Blue = S21 Actual Blue/Purple = S11 Actual

29 Laboratory Work Dark Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Aqua Blue = S21 Actual Blue/Purple = S11 Actual

30 Laboratory Work Aqua Blue = Ideal Dark Blue = S21 Simulated Red = S11 Simulated Purple = S21 Actual Blue/Purple = S11 Actual

31 Laboratory Work Aqua Blue = Ideal Red = S21 Simulated Dark Blue = S11 Simulated Purple = S21 Actual Blue/Purple = S11 Actual

32 Laboratory Work Light Blue = Ideal Red = S21 Simulated Aqua Blue = S11 Simulated Dark Blue = S21 Actual Purple = S11 Actual

33 Laboratory Work Aqua Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Dark Blue = S21 Actual Light Blue = S11 Actual

34 Laboratory Work

35

36 Preliminary Spring Semester Schedule WeekTask Winter BreakResearch and understand phase locked loop (PLL) theory and circuitry Begin design of PLL system Finalize filter design and simulations Begin implementing as parts arrive Full scale simulation of direct synthesis (DS) system Jan 19 – 25Design of PLL system DS system simulation Jan 26 – Feb 1Design PLL system DS system simulation Have all filters tested and built Feb 2 – 8Complete design of PLL system DS system simulation Feb 9 – 15Simulation of PLL system Complete DS system Simulation

37 Preliminary Spring Semester Schedule Feb 9 – 15Simulation of PLL system Complete DS system Simulation Feb 16 – 22Simulation of PLL system Feb 23 – 29Complete simulation of PLL system March 1 – 7Components Arrive, Begin Soldering, Testing, and Biasing Components March 8 – 14Physical implementation of DS March 15 – 21Physical implementation of DS, Spring Break? March 22 – 28Begin DS full scale testing March 29 – April 4DS full scale testing April 5 – 11Complete DS full scale testing April 12 – 18 April 19 – 25Student Expo April 26 – May 2Present successful findings

38 Revised Spring Semester Schedule March 1 – 7Generate PCB Layout for Components March 8 – 14Fabricate PCBs March 15 – 21Spring Break/Fabricate PCBs March 22 – 28Solder Components to PCBs March 29 – April 4System Testing April 5 – 11System Testing April 12 – 18 System Testing April 19 – 25System Testing/Student Expo April 26 – May 2Present successful findings

39 Delay Line Correlator Voltage output proportional to cos (wT) Power Splitter T L R I Cos (wt) RF cable with measure time delay = T

40 Fast Tuning Synthesizer Any questions?


Download ppt "Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:March 4, 2004."

Similar presentations


Ads by Google