1. 組合邏輯的函數 Functions of Combination Logic
Chapter 6
組合邏輯的函數 Functions of Combination Logic
基本的加法器
並聯二進位加法器
比較器
解碼器
編碼器
轉碼器
多工器(資料選擇器)
解多工器
同位元產生/檢查器 檢修
可程式邏輯
12. 以VHDL編寫邏輯函 數的程式

2. Figure 6--1 Logic symbol for a half-adder(半加器).
1. 基本的加法器
半加法器
Figure Logic symbol for a half-adder(半加器). A B
Carry
Sum 1
Thomas L. Floyd Digital Fundamentals, 8e

3. Figure 6--2 Half-adder logic diagram.
1. 基本的加法器
Figure Half-adder logic diagram. A B
Carry
Sum 1
Thomas L. Floyd Digital Fundamentals, 8e

4. Figure 6--3 Logic symbol for a full-adder (全加器).
1. 基本的加法器
全加法器
Figure Logic symbol for a full-adder (全加器).
Cin A B
Carry
Sum 1
Thomas L. Floyd Digital Fundamentals, 8e

5. Figure 6--4 Full-adder logic. Open file F06-04 to verify operation.
1. 基本的加法器
Figure Full-adder logic. Open file F06-04 to verify operation.
Cin A B
Carry
Sum 1
Thomas L. Floyd Digital Fundamentals, 8e

6. Figure 6--5 Full-adder implemented with half-adders.
以2個半加器來實做全加器
Figure Full-adder implemented with half-adders.
Thomas L. Floyd Digital Fundamentals, 8e

7. 1. 基本的加法器 例題 6-1 求 圖 6-6 所示的三個全加器的輸出 圖 6-6
例題 6-1 求 圖 6-6 所示的三個全加器的輸出
圖 6-6
Thomas L. Floyd Digital Fundamentals, 8e

8. 2. 二進位平行加法器
Figure Block diagram of a basic 2-bit parallel adder using two full-adders.
Thomas L. Floyd Digital Fundamentals, 8e

9. 2. 二進位平行加法器 例題 6-2 如圖6-8所示，當輸入的二進位數為101與011時，試求此3位元平行加法器的總合與進位輸出。
Figure 根據公式計算一下答案！
Thomas L. Floyd Digital Fundamentals, 8e

10. Figure 6--9 A 4-bit parallel adder.
2. 二進位平行加法器
四位元平行加法器
Figure A 4-bit parallel adder.
Thomas L. Floyd Digital Fundamentals, 8e

11. 進位傳遞(carry propagation)
進位產生 進位傳遞

12. 進位遞迴產生器 C0=輸入進位 C1=G0+P0C0 C2=G1+P1C1=G1+P1G0+P1P0C0
C3=G2+P2C2=G2+P2G2+P1P2G0+P2P1P0C0

13. Figure A--2 Four-bit parallel adders.
2. 二進位平行加法器
Figure A Four-bit parallel adders.
Thomas L. Floyd Digital Fundamentals, 8e

14. Figure A--3 Characteristics for the 74LS283. pp. A-3
2. 二進位平行加法器
Figure A Characteristics for the 74LS283. pp. A-3
Thomas L. Floyd Digital Fundamentals, 8e

15. 2. 二進位平行加法器

16. 四位元預見進位產生器

17. Figure 6--10 Examples of adder expansion.
2. 二進位平行加法器
Figure Examples of adder expansion.
Thomas L. Floyd Digital Fundamentals, 8e

18. 2. 二進位平行加法器 例題6-4 將兩個四位元平行加法器，連接成八位元平行加法器，求輸入下列數值後，所產生之輸出位元
Thomas L. Floyd Digital Fundamentals, 8e
Figure Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).

19. 2. 二進位平行加法器
應用範例： 簡單投票系統
Thomas L. Floyd Digital Fundamentals, 8e
Figure A voting system using full-adders and parallel binary adders.

20. Figure 6--13 Basic comparator operation.
3. 比較器
相等輸出
Figure Basic comparator operation.
Thomas L. Floyd Digital Fundamentals, 8e

21. 3. 比較器 A B F 1
Figure Logic diagram for equality comparison of two 2-bit numbers Open file F06-16 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e

22. 3. 比較器 例題6-5 求下列電路的輸出 Figure 6--15
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23. 3. 比較器
不相等輸出
1-bit comparator
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24. 3. 比較器 1
2-bit comparator
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25. 3. 比較器
Figure Logic symbol for a 4-bit comparator with inequality indication.
Thomas L. Floyd Digital Fundamentals, 8e

26. 3. 比較器
例題 6-6 求 Figure 6—17 的輸出
Thomas L. Floyd Digital Fundamentals, 8e

27. 3. 比較器
Figure A Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses). pp. A-4
Thomas L. Floyd Digital Fundamentals, 8e

28. 3. 比較器

29. Figure 6--19 An 8-bit magnitude comparator using two 74HC85s.
3. 比較器
Figure An 8-bit magnitude comparator using two 74HC85s.
Thomas L. Floyd Digital Fundamentals, 8e

30. 4. 解碼器
基本的二進制解碼器
Figure Decoding logic for the binary code 1001 with an active-HIGH output.
Thomas L. Floyd Digital Fundamentals, 8e

31. 4. 解碼器 例題6-8 試設計一個解碼器, 使得當輸入二進碼1011時, 輸出High
Figure Decoding logic for producing a HIGH output when 1011 is on the inputs.
Thomas L. Floyd Digital Fundamentals, 8e

32. 4. 解碼器
四位元解碼器
Figure Logic symbol for a 4-line-to-16-line (1-of-16) decoder Open file F06-24 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e

33. 4. 解碼器
Figure A—5a,b Pin diagram and logic symbol for the 74HC154 1-of-16 decoder. pp. A-5
Thomas L. Floyd Digital Fundamentals, 8e

34. 解多工器 CS1=0 輸出為沒作用 CS1=1 輸出由選擇線選到的為Low
Data selector
Data input
Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5
Thomas L. Floyd Digital Fundamentals, 8e

35. Figure 6--23 A 5-bit decoder using 74HC154s.
4. 解碼器
例題 6-9 某個應用電路需用五位元數值進行解碼，試使用兩個4對16線解碼器實作。
Figure A 5-bit decoder using 74HC154s.
Thomas L. Floyd Digital Fundamentals, 8e

36. 4. 解碼器
應用範例： 電腦輸入輸出裝置的選擇
Figure A simplified computer I/O port system with a port address decoder with only four address lines shown.
Thomas L. Floyd Digital Fundamentals, 8e

37. Figure 6--25 The 74HC42 BCD-to-decimal decoder.
4. 解碼器
例題 6-10 BCD轉十進位解碼器的邏輯圖如圖6-25，如果將圖6-26(a)的輸入波形施加到輸入端，求其輸出波形？
Figure The 74HC42 BCD-to-decimal decoder.
Thomas L. Floyd Digital Fundamentals, 8e

38. 4. 解碼器
Figure 6--26
Thomas L. Floyd Digital Fundamentals, 8e

39. 4. 解碼器
BCD轉7段顯示解碼器
Figure Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs. Open file F06-30 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e

40. 4. 解碼器
BI=Blank Input
RBI=Ripple BI
RBO=Ripple Blank Output
Light Test
Figure A Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver. pp. A-5
Thomas L. Floyd Digital Fundamentals, 8e

41. 4. 解碼器 Ripple Blanking (消零) 的用法
Figure A—7a Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6
Thomas L. Floyd Digital Fundamentals, 8e

42. 4. 解碼器 Ripple Blanking (消零) 的用法
Figure A—7b Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6
Thomas L. Floyd Digital Fundamentals, 8e

43. Figure 6--28 Logic symbol for a decimal-to-BCD encoder.
5. 編碼器
十進位轉BCD編碼器
Figure Logic symbol for a decimal-to-BCD encoder.
Thomas L. Floyd Digital Fundamentals, 8e

44. Figure 6--29 Basic logic diagram of a decimal-to-BCD encoder.
沒有優先權編碼的缺點：兩輸入同時active會出錯
Figure Basic logic diagram of a decimal-to-BCD encoder.
A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.
Thomas L. Floyd Digital Fundamentals, 8e

45. 編碼器
編碼器:解碼器的反函數
8到3優先權編碼器:

46. 8到3優先權編碼器 c=y7y6y5y4y3y2y1+y7y6y5y4y3+y7y6y5+y7
b=y7y6y5y4y3y2+y7y6y5y4y3+y7y6+y7
=y7+y6+y5y4y3+y5y4y2
a=y7y6y5y4+y7y6y5+y7y6+y7
=y7+y6+y5+y4

47. 8到3優先權編碼器
y7 y6 y5 y4 y3 y2 y1 y0 a b c

48. 10進位轉BCD編碼器
Figure A Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority). pp. A-7
Thomas L. Floyd Digital Fundamentals, 8e

49. 5. 編碼器
8對3線 編碼器
No Input Low  EO=low
EI=Low 
At least one Input Low  GS=low
Figure A Logic symbol for the 74F148 8-line-to-3-line encoder. pp. A-8
Thomas L. Floyd Digital Fundamentals, 8e

50. 5. 編碼器
8~15 pin No Input Low
 EO=low
EI=Low 
At least one Input Low  GS=low
Figure A A 16-line-to-4 line encoder using 74F148s and external logic. pp. A-8
Thomas L. Floyd Digital Fundamentals, 8e

51. Figure 6--30 A simplified keyboard encoder.
提升電阻(pull-up resistor):
確保無按鍵時，輸出仍為High
應用範例： 鍵盤編碼器
Figure A simplified keyboard encoder.
Thomas L. Floyd Digital Fundamentals, 8e

52. Binary轉Gray 轉碼器 Gray 轉Binary 轉碼器
Figure Four-bit binary-to-Gray conversion logic. Open file F06-39 to verify operation.
Figure Four-bit Gray-to-binary conversion logic. Open file F06-40 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e

53. Figure 6--33
Thomas L. Floyd Digital Fundamentals, 8e

54. 7. 多工器(資料選擇器)
解多工器
Data selector
CS1=Low 則有輸出0 , 否則為 1
Data input
Figure Logic symbol for a 1-of-4 data selector/multiplexer. pp. A-8
Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5
Thomas L. Floyd Digital Fundamentals, 8e
Thomas L. Floyd Digital Fundamentals, 8e

55. 7. 多工器(資料選擇器)
Figure Logic diagram for a 4-input multiplexer. Open file F06-43 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e

56. 7. 多工器(資料選擇器)
Figure 6--36
Thomas L. Floyd Digital Fundamentals, 8e

57. 7. 多工器(資料選擇器)
Figure A Pin diagram and logic symbol for the 74HC A quadruple 2-input data selector/multiplexer. pp. A-9 i.e. 4-bit multiplexer (同時選1A~4A(G1=0時, Y=A) 或 1B~4B(G1=1 時,Y=B) )
Thomas L. Floyd Digital Fundamentals, 8e

58. 7. 多工器(資料選擇器)
Figure A Pin diagram and logic symbol for the 74LS151 8-input data selector/multiplexer. pp. A-10
Thomas L. Floyd Digital Fundamentals, 8e

59. Figure 6--37 A 16-input multiplexer.
7. 多工器(資料選擇器)
Figure A 16-input multiplexer.
Thomas L. Floyd Digital Fundamentals, 8e

60. Figure 6--38 Simplified 7-segment display multiplexing logic.
Thomas L. Floyd Digital Fundamentals, 8e
Figure Simplified 7-segment display multiplexing logic.

61. Yin A2 A1 A0
Yout 1 2 3 4 5 6 7
Figure Data selector/multiplexer connected as a variable logic function generator.
Thomas L. Floyd Digital Fundamentals, 8e

62. Yin A3 A2 A1 A0
Yout 1 2
A0' 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure Data selector/multiplexer connected as a 4-variable logic function generator.
Thomas L. Floyd Digital Fundamentals, 8e

63. Figure 6--41 A 1-line-to-4-line demultiplexer.
8.解多工器
Figure A 1-line-to-4-line demultiplexer.
Figure 6--42
Thomas L. Floyd Digital Fundamentals, 8e

64. Figure A—5c The 74HC154 decoder used as a de-multiplexer. pp. A-5
8.解多工器
Figure A—5c The 74HC154 decoder used as a de-multiplexer. pp. A-5
Thomas L. Floyd Digital Fundamentals, 8e

65. 基本同位元邏輯
Figure 6--43
Thomas L. Floyd Digital Fundamentals, 8e

66. Figure 6--44 The 74LS280 9-bit parity generator/checker.
同位元產生/檢查器
Even parity checker
Odd parity generator
Figure The 74LS280 9-bit parity generator/checker.
Thomas L. Floyd Digital Fundamentals, 8e

67. Figure 6--45 Simplified data transmission system with error detection.
用Decoder
當DeMUX用
Figure Simplified data transmission system with error detection.
Thomas L. Floyd Digital Fundamentals, 8e

68. 9. 同位元產生/檢查器
Figure Example of data transmission with and without error for the system in Figure 6-45.
Thomas L. Floyd Digital Fundamentals, 8e

69. Figure 6--47 Decoder waveforms with output glitches.
10. 檢修
Figure Decoder waveforms with output glitches.
Thomas L. Floyd Digital Fundamentals, 8e

70. 10. 檢修
Figure Decoder waveform displays showing how transitional input states produce glitches in the output waveforms.
Thomas L. Floyd Digital Fundamentals, 8e

71. 10. 檢修 去除Glitch的方法之一, 就是用Strobe
Figure Application of a strobe waveform to eliminate glitches on decoder outputs.
Thomas L. Floyd Digital Fundamentals, 8e

72. Figure 6--61 Typical configuration for conventional PLD programming.
11. 可程式邏輯
Figure Typical configuration for conventional PLD programming.
Thomas L. Floyd Digital Fundamentals, 8e

73. 位元向量(Bit Vectors)與陣列( Arrays)
12. 以VHDL編寫邏輯函數的程式
位元向量(Bit Vectors)與陣列( Arrays)
位元向量(bit_vector)資料型別允許將若干位元編組成一個陣列。
陣列是具有單一識別字，並且由個別元素所組合的有序集合。
陣列中每一個元素都共用一個識別字，並利用數字索引(index)去存取陣列中元素。
例如：假如以bit vector資料型別去宣告識別字A ，則我們可以A(0) 存取A中第一個元素，以A(1)存取A中下一個元素。
Port(A: in bit_vector(0 to 7)); 表示輸入埠有8個輸入: A(0), A(1), A(2), … A(7)

74. BCD to 7 segment display decoder
X(0)
X(1)
X(2)
X(3)
X(4)
X(5)
X(6)

75. BCD to 7 segment display 解碼器使用資料流描述法
entity BCD_to_seven_segment is
port( A: in bit_vector(0 to 3): X: out bit_vector(0 to 6));
end entity BCD_to_seven_segment
architecture decoder of BCD_to_seven_segment is
begin
X(0) <= (not A(1) and not A(3)) or (not A(1) and A(2)) or (A(1) and A(3)) or A(0);
X(1)<= (not A(2) and not A(3)) or (A(2) and A(3)) or not A(1);

76. BCD to 7 segment display 解碼器使用資料流描述法（續）
X(2)<= A(1) or A(3) or not A(2)
X(3) <= (not A(1) and A(2)) or (A(1) and not A(2) and A(3)) or (A(2) and not A(3)) or (not A(1) and not A(3));
X(4) <= (A(2) and not A(3)) or (not A(1) and not A(3));
X(5) <= (not A(2) and not A(3)) or (A(1) and not A(2)) or (A(1) and not A(3)) or A(0);
X(6) <= (A(1) xor A(2)) or A(0);
end architecture decoder

77. -- 全加器使用資料流描述法.
entity FULLADDER is
port (X: in bit; Y: in bit; Cin: in bit;
Cout: out bit; Sum: out bit);
end FULLADDER;
architecture full_adder_logic of FULLADDER is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end full_adder_logic;

78. 全加器測試

79. End of Chapter 6